XQR5VFX130-1CF1752V of Xilinx Virtex-5QV FPGA

XQR5VFX130-1CF1752V FPGAs Overview

Radiation-hardened Virtex®-5QV FPGAs are available in the -1 speed grade only. Virtex-5QV FPGA DC and AC characteristics are specified for military temperatures.

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical conditions.

Features

This section briefly describes the features of the Virtex-5QV family of FPGAs.
Input/Output Blocks (SelectIO Resources)
IOBs are programmable and can be categorized as follows:
• Programmable single-ended or differential (LVDS) operation
• Input block with an optional single data rate (SDR) or double data rate (DDR) register
• Output block with an optional SDR or DDR register
• Bidirectional block
• Per-bit deskew circuitry
• Dedicated I/O and regional clocking resources
• Built-in data serializer/deserializer
The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.
IOBs support the following single-ended standards:
• LVTTL
• LVCMOS (3.3V, 2.5V, 1.8V, 1.5V, and 1.2V)
• PCI (33 and 66 MHz)
• PCI-X
• GTL and GTLP
• HSTL 1.5V and 1.8V (Class I, II, III, and IV)
• HSTL 1.2V (Class 1)
• SSTL 1.8V and 2.5V (Class I and II)
The Digitally Controlled Impedance (DCI) I/O feature can be configured to provide on-chip termination for each single-ended
I/O standard and some differential I/O standards.
The IOB elements also support these differential signaling I/O standards:
• LVDS and Extended LVDS (2.5V only)
• BLVDS (Bus LVDS)
• ULVDS
• HyperTransport™ technology
• Differential HSTL 1.5V and 1.8V (Class I and II)
• Differential SSTL 1.8V and 2.5V (Class I and II)
• RSDS (2.5V point-to-point)

Applications

Radiation-Hardness Assurance
The radiation-hardened, space-grade Virtex-5QV FPGAs are guaranteed for total ionizing dose (TID) life and single-event
latch-up (SEL) immunity. Extensive single-event upset (SEU) characterization is performed and reported by the Xilinx
Radiation Test Consortium (XRTC).
Total Ionizing Dose
Each wafer lot is sampled and tested per Method 1019 to assure that device performance meets or exceeds the guaranteed
DC electrical specification requirements, as well as AC and timing parameters at maximum guaranteed total dose levels.
Single-Event Latch-Up
The radiation-hardened Virtex-5QV FPGA technology incorporates a thin epitaxial layer in the wafer manufacturing process
for latch-up immunity assurance. The qualified mask set is verified in a heavy ion environment under vacuum, and tested at
maximum VCC and maximum operating temperature, to a fluence exceeding 1E8 particles/cm2.

FAQ

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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Xilinx XQR5VFX130 Development Boards, Evaluation Boards, or Virtex-5QV FPGA Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain XQR5VFX130-1CF1752V technical support documents?
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