XQ4062XL-3PGG475N of Xilinx Memory - Configuration Proms for FPGA's

XQ4062XL-3PGG475N FPGAs Overview

For more information refer to Xilinx XQ4062XL-3PGG475N Programmable Gate Arrays product specification. This data sheet contains pinout tables for XQ4010E only. Refer to Xilinx web site for pinout tables for other devices. (Pinouts for XQ4000E/EX are identical to XC4000E/EX.)

(http://www.xilinx.com/partinfo/databook.htm)

Features

For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html
System featured Field-Programmable Gate Arrays

Synchronous write option
Dual-port RAM option
Select-RAMTM memory: on-chip ultra-fast RAM with
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution networks

System Performance beyond 60 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features

IEEE 1149.1-compatible boundary scan logic support
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12 mA sink current per XQ4000E/EX output

Configured by Loading Binary File

Unlimited reprogrammability

Readback Capability

Program verification
Internal node observability

Available Speed Grades:

XQ4000E -3 for plastic packages only
-4 for ceramic packages only
XQ4028EX -4 for all packages

FAQ

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