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FPGAKey Technical Documents
Download DatasheetThe XQ2V3000-4FF1152N is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces.
The leading-edge 0.15 µm / 0.12 µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the XQ2V3000-4FF1152N enhances programmable logic design capabilities and is a powerful alternative to mask-programmed gates arrays.
• Industry’s first military-grade platform FPGA solution
• Certified to MIL-PRF-38535 (Qualified Manufacturer Listing)
• 100% factory tested
• Guaranteed over the full military temperature range
(–55°C to +125°C) or industrial temperature range
(–40°C to +100°C)
• Ceramic and plastic wire-bond and flip-chip grid array packages
• IP-immersion architecture
• Densities from 1M to 6M system gates
• 300+ MHz internal clock speed (Advance Data)
• 622+ Mb/s I/O (Advance Data)
• SelectRAM Memory Hierarchy
• 2.5 Mb of dual-port RAM in 18 Kbit block SelectRAM resources
• Up to 1 Mb of distributed SelectRAM resources
• High-performance interfaces to external memory
• High-performance clock management circuitry
• Up to 12 DCM (Digital Clock Manager) modules
- Precise clock de-skew
- Flexible frequency synthesis
- High-resolution phase shifting
• 16 global clock multiplexer buffers
• Active interconnect technology
• Fourth-generation segmented routing structure
• Predictable, fast routing delay, independent of fanout
• SelectIO-Ultra Technology
• Up to 824 user I/Os
• 19 single-ended and six differential standards
• Programmable sink current (2 mA to 24 mA) per I/O
• Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards
• PCI compliant (32/33 MHz) at 3.3V
• Differential signaling
• 622 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers
• Bus LVDS I/O
• Lightning Data Transport (LDT) I/O with current driver buffers
• Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O
• Built-in DDR input and output registers
• Proprietary high-performance SelectLink Technology
- High-bandwidth data path
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