XCZU21DR-2FFVD1156E of Xilinx Zynq UltraScale+ RFSoC

XCZU21DR-2FFVD1156E FPGAs Overview

The XCZU21DR-2FFVD1156E of Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bit quad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system.

The XCZU21DR-2FFVD1156E of three generations of Zynq UltraScale+ RFSoCs integrate up to 16 channels of RF-ADCs and RF-DACs, all with excellent noise spectral density. The RF data converters also include power efficient digital down converters (DDCs) and digital up converters (DUCs) that include programmable interpolation and decimation, NCO, and complex mixer. The DDCs and DUCs can also support dual-band operation. See Table 1 for key features and sample rates.

Features

RF Data Converter Subsystem Overview

The XCZU21DR-2FFVD1156Einclude an RF data converter subsystem, which contains multiple radio frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be individually configured for real data or can be configured in pairs for real and imaginary I/Q data.

Soft Decision Forward Error Correction (SD-FEC) Overview

The XCZU21DR-2FFVD1156E include highly flexible soft-decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.

Processing System Overview

The XCZU21DR-2FFVD1156E feature a quad-core Arm Cortex-A53 (APU) with a dual-core Arm Cortex-R5 (RPU) processing system (PS). High-bandwidth connectivity based on the Arm AMBA AXI4 protocol connects the processing units with the peripherals and provides interface between the PS and the programmable logic (PL).

I/O, Transceiver, PCIe, 100G Ethernet, and 150G Interlaken

Data is transported on and off chip through a combination of the high-performance parallel SelectIO interface and high-speed serial transceiver connectivity. I/O blocks provide support for cutting-edge memory interface and network protocols through flexible I/O standard and voltage support. The serial transceivers in the UltraScale architecture-based devices transfer data up to 28.21Gb/s, enabling 25G+ backplane designs with dramatically lower power per bit than previous generation transceivers. All transceivers, except the PS-GTR, support the required data rates for 8.0GT/s (Gen3) and 16.0GT/s (Gen4) for PCIe. The integrated blocks for PCIe can be configured as either Endpoint or Root Port, supporting a variety of link widths and speeds depending on the targeted device speed grade and package. Integrated blocks for 150Gb/s Interlaken and 100Gb/s Ethernet (100G MAC/PCS) extend the capabilities of UltraScale devices, enabling simple, reliable support for Nx100G switch and bridge applications.

Clocks and Memory Interfaces

The XCZU21DR-2FFVD1156E contain powerful clock management circuitry, including clock synthesis, buffering, and routing components that together provide a highly capable framework to meet design requirements. The clock network allows for extremely flexible distribution of clocks to minimize the skew, power consumption, and delay associated with clock signals. The clock management technology is tightly integrated with dedicated memory interface circuitry to enable support for high-performance external memories, including DDR4. In addition to parallel memory interfaces, XCZU21DR-2FFVD1156E support serial memories, such as hybrid memory cube (HMC).

Routing, Logic, Storage, and Signal Processing

Configurable logic blocks (CLBs) containing 6-input look-up tables (LUTs) and flip-flops, DSP slices with 27x18 multipliers, 36Kb block RAMs with built-in FIFO and ECC support, and 4Kx72 UltraRAM blocks are all connected with an abundance of high-performance, low-latency interconnect. In addition to logical functions, the CLB provides shift register, multiplexer, and carry logic functionality as well as the ability to configure the LUTs as distributed memory to complement the highly capable and configurable block RAMs. The DSP slice, with its 96-bit-wide XOR functionality, 27-bit pre-adder, and 30-bit A input, performs numerous independent functions including multiply accumulate, multiply add, and pattern detect.

Configuration, Encryption, and System Monitoring

The XCZU21DR-2FFVD1156E are booted via the configuration security unit (CSU), which supports secure boot via the 256-bit AES-GCM and SHA/384 blocks. The cryptographic engines in the CSU can be used in the RFSoC after boot for user encryption. The System Monitor enables the monitoring of the physical environment via on-chip temperature and supply sensors and can also monitor up to 17 external analog inputs.

FAQ

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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
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Q: Where can I purchase Xilinx XCZU21DR Development Boards, Evaluation Boards, or Zynq UltraScale+ RFSoC Starter Kit? also provide technical information?
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