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FPGAKey Technical Documents
Download DatasheetThe XCV3200E-7CGG1156I delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 μm CMOS process.
the XCV3200E-7CGG1156I delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be individually configured for real data or can be configured in pairs for real and imaginary I/Q data.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding data as a means to control errors in data transmission over unreliable or noisy communication channels. The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in 5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU) with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm Mali-400 MP2 graphics processing unit (GPU).
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FPGA VIRTEX -E FAMILY 876.096K GATES 73008 CELLS COMMERCIAL CMOS TECHNOLOGY 1.8V 156-PIN CBGA
FPGA Virtex-E Family 876.096K Gates 73008 Cells 400MHz 0.18um Technology 1.8V 1156-Pin CBGA
FPGA Virtex-E Family 876.096K Gates 73008 Cells 400MHz 0.18um Technology 1.8V 1156-Pin FBGA
FPGA Virtex-E Family 876.096K Gates 73008 Cells 400MHz 0.18um Technology 1.8V 1156-Pin FBGA
5+ $68.3400
7+ $67.3200
20+ $66.3000
30+ $65.2800
50+ $64.2600
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