XCR5128-10VQ100C of Xilinx Macrocell CPLD

XCR5128-10VQ100C FPGAs Overview

The XCR5128-10VQ100C CPLD (Complex Programmable Logic Device) is the third in a family of CoolRunner CPLDs from Xilinx. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique, the XCR5128-10VQ100C offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for ‘turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Xilinx also offers the high-speed XCR3128 CPLD that offers these features in a full 3V implementation.

The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.

The XCR5128-10VQ100C CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). The XCR5128-10VQ100C CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The XCR5128-10VQ100C also includes an industry-standard, IEEE 1149.1, JTAG interface through which in-system programming (ISP) and reprogramming of the device is supported.

The Xilinx Macrocell CPLD series XCR5128-10VQ100C is 128 Macrocell CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

• Industry's first TotalCMOS PLD - both CMOS design and process technologies
• Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
• IEEE 1149.1-compliant, JTAG Testing Capability
- Four pin JTAG interface (TCK, TMS, TDI, TDO)
- IEEE 1149.1 TAP Controller
- JTAG commands include: Bypass, Sample/Preload,Extest, Usercode, Idcode, HighZ
• 5V, In-System Programmable (ISP) using the JTAG interface
- On-chip supervoltage generation
- ISP commands include: Enable, Erase, Program, Verify
- Supported by multiple ISP programming platforms
• High speed pin-to-pin delays of 7.5 ns
• Ultra-low static power of less than 100 µA
• 100% routable with 100% utilization while all pins and all macrocells are fixed
• Deterministic timing model that is extremely simple to use
• Four clocks available
• Programmable clock polarity at every macrocell
• Support for asynchronous clocking
• Innovative XPLA architecture combines high speed with extreme flexibility
• 1000 erase/program cycles guaranteed
• 20 years data retention guaranteed
• Logic expandable to 37 product terms
• PCI compliant
• Advanced 0.5µ E2CMOS process
• Security bit prevents unauthorized access
• Design entry and verification using industry standard and Xilinx CAE tools
• Reprogrammable using industry standard device programmers
• Innovative Control Term structure provides either sum terms or product terms in each logic block for:
- Programmable 3-state buffer
- Asynchronous macrocell register preset/reset
• Programmable global 3-state pin facilitates "bed of nails" testing without using logic resources
• Available in PLCC, VQFP, and PQFP packages
• Available in both Commercial and Industrial grades

FAQ

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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Xilinx XCR5128 Development Boards, Evaluation Boards, or Macrocell CPLD Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain XCR5128-10VQ100C technical support documents?
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Q: What should I do if I did not receive the technical support for XCR512810VQ100C in time?
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