The XCR3512XL-12QPQ208CMN is targeted for low power systems that include portable, handheld, and power sensitive applications.，includes Fast Zero Power (FZP) design technology that combines low power and high speed. With this design technique, the XCR3512XL-12QPQ208CMN offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power that is less than 56 μW at standby without the need for "turbo bits" or other power down schemes.
By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD. XCR3512XL-12QPQ208CMN devices are the only TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The FZP design technique combines fast nonvolatile memory cells with ultra-low power SRAM shadow memory to deliver the industry’s lowest power 3.3V CPLD family.
CoolRunner XPLA3 CPLDs are supported by Xilinx WebPACK software and industry standard CAE tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, Viewlogic, and Synplicity), using HDL editors with ABEL, VHDL, and Verilog, and/or schematic capture design entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on multiple personal computer (PC), Sun, and HP platforms.The XCR3512XL-12QPQ208CMN is electrically reprogrammable using industry standard device programmers.
Fast Zero Power (FZP) design technique provides ultra-low power and very high speed
Typical Standby Current of 17 to 18 μA at 25°C
Innovative CoolRunner XPLA3 architecture combines high speed with extreme flexibility
Based on industry`s first TotalCMOS PLD — both CMOS design and process technologies
Advanced 0.35μ five layer metal EEPROM process
1,000 erase/program cycles guaranteed
20 years data retention guaranteed
3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface
Full Boundary-Scan Test (IEEE 1149.1)
Fast programming times
Support for complex asynchronous clocking
16 product term clocks and four local control term clocks per function block
Four global clocks and one universal control term clock per device
Excellent pin retention during design changes
Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade
5V tolerant I/O pins
Four output enable controls per function block
Foldback NAND for synthesis optimization
Universal 3-state which facilitates "bed of nails" testing
Available in Chip-scale BGA, Fineline BGA, and QFP packages. Pb-free available for most package types. See Xilinx Packaging for more information.
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