XCR3064XL-6CPG56C of Xilinx Macrocell CPLD

XCR3064XL-6CPG56C FPGAs Overview

The CoolRunner™ XPLA3 XCR3064XL-6CPG56C device is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are as fast as 5.5 ns with a maximum system frequency of 192 MHz.

The Xilinx CPLDs series XCR3064XL-6CPG56C is XCR3064XL-6CPG56C - NOT RECOMMENDED for NEW DESIGN, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

Low power 3.3V 64 macrocell CPLD
5.5 ns pin-to-pin logic delays
System frequencies up to 192 MHz
64 macrocells with 1,500 usable gates
Available in small footprint packages
- 44-pin VQFP (36 user I/O pins)
- 48-ball CS BGA (40 user I/O pins)
- 56-ball CP BGA (48 user I/O pins)
- 100-pin VQFP (68 user I/O pins)
Optimized for 3.3V systems
- Ultra-low power operation
- Typical Standby Current of 17 μA at 25°C
- 5V tolerant I/O pins with 3.3V core supply
- Advanced 0.35 micron five layer metal EEPROM process
- Fast Zero Power CMOS design technology
- 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Advanced system features
- In-system programming
- Input registers
- Predictable timing model
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clocks
- Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for architecture description

FAQ

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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Xilinx XCR3064XL Development Boards, Evaluation Boards, or Macrocell CPLD Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain XCR3064XL-6CPG56C technical support documents?
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Application Field

Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment

XCR3064XL-6CPG56C Specifications

Specification	Value
Programmable Type	In System Programmable (min 1K program/erase cycles)
Delay Time tpd(1) Max	5.5ns
Voltage Supply - Internal	3V ~ 3.6V
Number of Logic Elements/Blocks	4
Number of Macrocells	64
Number of Gates	1500
Number of I/O	48
Operating Temperature	0℃ ~ 70℃ (TA)
Mounting Type	Surface Mount
Package / Case	56-LFBGA, CSPBGA
Supplier Device Package	56-CSBGA (6x6)