$12.505 - $7.353 | 1 Pieces(Min. Order)
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FPGAKey Technical Documents
Download DatasheetThe XCR3064XL-6CP56I device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz.
The XCR3064XL-6CP56I offer a TotalCMOS solution,
both in process technology and design technique. These
CPLDs employ a cascade of CMOS gates to implement
their sum of products, instead of the traditional sense amp
approach.
Low power 3.3V 64 macrocell CPLD
5.5 ns pin-to-pin logic delays
System frequencies up to 192 MHz
64 macrocells with 1,500 usable gates
Available in small footprint packages
44-pin VQFP (36 user I/O pins)
48-ball CS BGA (40 user I/O pins)
56-ball CP BGA (48 user I/O pins)
100-pin VQFP (68 user I/O pins)
Optimized for 3.3V systems
Ultra-low power operation
Typical Standby Current of 17 μA at 25°C
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM process
Fast Zero Power CMOS design technology
3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Advanced system features
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
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