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CPLD CoolRunner XPLA3 Family 1.5K Gates 64 Macro Cells 95MHz 0.35um Technology 3.3V 56-Pin CSBGA
The XCR3064XL-10CP56C CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR3064XL-10CP56C offers true pin-to-pin speeds of 10 ns, while simultaneously delivering power that is less than 50 µA at standby without the need for “turbo-bits” or other power-down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any other CPLD.
These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Xilinx also offers the high speed XCR5064 CPLD that offers these features in a full 5V implementation. The Xilinx FZP CPLDs utiize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 10 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block.
This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 12.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density.
The XCR3064XL-10CP56C CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). The XCR3064XL-10CP56C CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others.The XILINX CPLDs series XCR3064XL-10CP56C is XCR3064XL 64 Macrocell CPLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
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In System Programmable (min 1K program/erase cycles)
Delay Time tpd(1) Max
Voltage Supply - Internal
3V ~ 3.6V
Number of Logic Elements/Blocks
Number of Macrocells
Number of Gates
Number of I/O
0??C ~ 70??C (TA)
Package / Case
Supplier Device Package