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FPGAKey Technical Documents
Download DatasheetThe XCR3032XL-7VQ44CES device is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 154 MHz.
TotalCMOS Design Technique for Fast Zero Power
The XCR3032XL-7VQ44CES offer a TotalCMOS solution, both in process technology and design technique. These CPLDs employ a cascade of CMOS gates to implement their sum of products, instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx CPLDs to offer devices that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance.
Ultra-low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM process
Fast Zero Power (FZP) CMOS technology
3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O, no minimum clock input capacitance)
Advanced system features
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
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416+ $11.19
832+ $10.3792
1664+ $8.7574
2496+ $7.9465
3328+ $7.2005
4160+ $6.3248
41600+ $5.9356
416+ $9.3563
832+ $8.6783
1664+ $7.3224
2496+ $6.6444
3328+ $6.0206
4160+ $5.2884
41600+ $4.9629
416+ $11.19
832+ $10.3792
1664+ $8.7574
2496+ $7.9465
3328+ $7.2005
4160+ $6.3248
41600+ $5.9356
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