Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1, page 2). The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2, page 2).
When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. Refer to "AC Electrical Characteristics," page 16 for timing considerations.
A summary of the Platform Flash PROM family members and supported features is shown in Table 1.
Table 1: Platform Flash PROM FeaturesDeviceDensity (Mb)VCCINT (V)VCCO Range (V)VCCO Range (V)PackagesProgram In-system via JTAGSerial Config.Parallel Config.Design RevisioningCompressionXCF01S13.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF02S23.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF04S43.31.8 – 3.32.5 – 3.3VO20/VOG20 Yes Yes XCF08P81.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes(1) YesXCF16P161.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes YesXCF32P321.81.8 – 3.32.5 – 3.3VO48/VOG48 FS48/FSG48 Yes Yes Yes Yes Yes The Xilinx EEPROM series XCF01SVOG20C is PROM, PLATFORM FLASH, 1MBIT, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
• In-System Programmable PROMs for Configuration of Xilinx FPGAs
• Low-Power Advanced CMOS NOR Flash Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range (–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA Configuration
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