XC9572-15PC84C of Xilinx High-performance CPLD

XC9572-15PC84C FPGAs Overview

Description：
The XC9572-15PC84C is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

Features：

• 7.5 ns pin-to-pin logic delays on all pins
• fCNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells within Function Block
- Global and product term clocks, output enables, set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
• Programmable power reduction mode in each macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages

Features

72 macrocells with 1,600 usable gates
Available in small footprint packages

44-pin VQFP (34 user I/O pins)
100-pin TQFP (72-user I/O pins)

Optimized for high-performance 2.5V systems

Low power operation
Multi-voltage operation

Advanced system features

In-system programmable
Superior pin-locking and routability with Fast CONNECT II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with individual product-term allocation
Local clock inversion with three global and one product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)

Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability

20 year data retention
ESD protection exceeding 2,000V

FAQ

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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Xilinx XC9572 Development Boards, Evaluation Boards, or High-Performance CPLD Starter Kit? also provide technical information?
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Q: How to obtain XC9572-15PC84C technical support documents?
Enter the "XC9572-15PC84C" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for XC957215PC84C in time?
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Application Field

Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment

XC9572-15PC84C Specifications

Specification	Value
Supply Voltage (DC)	5.00 V
Number of I/O Pins	69
Product Lifecycle Status	Obsolete
Packaging	Bulk
Mounting Style	Surface Mount
Number of Pins	84
Case/Package	PLCC
RoHS	Compliant
Lead-Free Status	Contains Lead