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FPGAKey Technical Documents
Download DatasheetThe XC95108-7PQ100I is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns.
Power dissipation can be reduced in the XC95108-7PQ100I by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.
Operating current for each design can be approximated for specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
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Specification | Value |
---|---|
Programmable Type | In System Programmable (min 10K program/erase cycles) |
Delay Time tpd(1) Max | 7.5ns |
Voltage Supply - Internal | 4.5V ~ 5.5V |
Number of Logic Elements/Blocks | 6 |
Number of Macrocells | 108 |
Number of Gates | 2400 |
Number of I/O | 81 |
Operating Temperature | -40℃ ~ 85℃ (TA) |
Mounting Type | Surface Mount |
Package / Case | 100-BQFP |
Supplier Device Package | 100-PQFP (20x14) |
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