XC7Z100-2FFG900I of Xilinx Zynq-7000 SoC

XC7Z100-2FFG900I FPGAs Overview

Zynq-7000 SoC First Generation Architecture
The Zynq®-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core or single-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
Processing System (PS) ARM Cortex-A9 Based
● Application Processor Unit (APU)
• 2.5 DMIPS/MHz per CPU
• CPU frequency: Up to 1 GHz
• Coherent multiprocessor support
• ARMv7-A architecture
- TrustZone® security
- Thumb®-2 instruction set
• Jazelle® RCT execution Environment Architecture
• NEON™ media-processing engine
• Single and double precision Vector Floating Point Unit (VFPU)
• CoreSight™ and Program Trace Macrocell (PTM)
• Timer and Interrupts
- Three watchdog timers
- One global timer
- Two triple-timer counters
● Caches
• 32 KB Level 1 4-way set-associative instruction and data caches
(independent for each CPU)
• 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
• Byte-parity support
● On-Chip Memory
• On-chip boot ROM
• 256 KB on-chip RAM (OCM)
• Byte-parity support
● External Memory Interfaces
• Multiprotocol dynamic memory controller
• 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories
• ECC support in 16-bit mode
• 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories
• Static memory interfaces
- 8-bit SRAM data bus with up to 64 MB support
- Parallel NOR flash support
- ONFI1.0 NAND flash support (1-bit ECC)
- 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash
● 8-Channel DMA Controller
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support
● I/O Peripherals and Interfaces
• Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
- Scatter-gather DMA capability
- Recognition of 1588 rev. 2 PTP frames
- GMII, RGMII, and SGMII interfaces
• Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints
- USB 2.0 compliant device IP core
- Supports on-the-go, high-speed, full-speed, and low-speed modes
- Intel EHCI compliant USB host
- 8-bit ULPI external PHY interface
• Two full CAN 2.0B compliant CAN bus interfaces
- CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant
- External PHY interface
• Two SD/SDIO 2.0/MMC3.31 compliant controllers
• Two full-duplex SPI ports with three peripheral chip selects
• Two high-speed UARTs (up to 1 Mb/s)
• Two master and slave I2C interfaces
• GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the Programmable Logic
• Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments
● Interconnect
• High-bandwidth connectivity within PS and between PS and PL
• ARM AMBA® AXI based
• QoS support on critical masters for latency and bandwidth control
The Xilinx Microprocessors series XC7Z100-2FFG900I is MPU XC7Z100 32-Bit 1000MHz 900-Pin FFG (Alt: XC7Z100-2FFG900I), View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

Configurable Logic Blocks (CLB)
• Look-up tables (LUT)
• Flip-flops
• Cascadeable adders
36 Kb Block RAM
• True Dual-Port
• Up to 72 bits wide
• Configurable as dual 18 Kb block RAM
DSP Blocks
• 18 x 25 signed multiply
• 48-bit adder/accumulator
• 25-bit pre-adder
Programmable I/O Blocks
• Supports LVCMOS, LVDS, and SSTL
• 1.2V to 3.3V I/O
• Programmable I/O delay and SerDes

FAQ

Q: Does the price of XC7Z100-2FFG900I devices fluctuate frequently?
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No, only submit the quantity, email address and other contact information required for the inquiry of XC7Z100-2FFG900I, but you need to sign up for the post comments and resource downloads.
Q: How can I obtain software development tools related to the Xilinx FPGA platform?
In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Xilinx XC7Z100 Development Boards, Evaluation Boards, or Zynq-7000 SoC Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain XC7Z100-2FFG900I technical support documents?
Enter the "XC7Z100-2FFG900I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for XC7Z1002FFG900I in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the XC7Z100-2FFG900I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment

Technical Attributes

Architecture

MCU, FPGA
Core Processor

Dual ARM? Cortex?-A9 MPCore? with CoreSight?
RAM Size

256KB
Peripherals

DMA
Connectivity

CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG
Speed

800MHz