The Zynq-7000 family XC7Z007S-1CLG225C is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core or single-core ARM Cortex-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
The XC7Z007S-1CLG225C SoCs are available in -3, -2, -2LI, -1, and -1LQ speed grades, with -3 having the highest performance. The -2LI devices operate at programmable logic (PL) VCCINT/VCCBRAM = 0.95V and are screened for lower maximum static power. The speed specification of a -2LI device is the same as that of a -2 device. The -1LQ devices operate at the same voltage and speed as the -1Q devices and are screened for lower power. Zynq XC7Z007S-1CLG225C device DC and AC characteristics are specified in commercial, extended, industrial, and expanded (Q-temp) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in the commercial, extended, or industrial temperature ranges. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications.The Xilinx Embedded - System On Chip (SoC) series XC7Z007S-1CLG225C is PSoC / MPSoC Microprocessor, Zynq-7000 Family, ARM Cortex-A9, 667 MHz, BGA-225, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
Configurable Logic Blocks (CLB)
• Look-up tables (LUT)
• Cascadeable adders
36 Kb Block RAM
• True Dual-Port
• Up to 72 bits wide
• Configurable as dual 18 Kb block RAM
• 18 x 25 signed multiply
• 48-bit adder/accumulator
• 25-bit pre-adder
Programmable I/O Blocks
• Supports LVCMOS, LVDS, and SSTL
• 1.2V to 3.3V I/O
• Programmable I/O delay and SerDes
Internet of Things
Single ARM? Cortex?-A9 MPCore? with CoreSight?
CANbus, EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART/USART, USB OTG
Artix?-7 FPGA, 23K Logic Cells
0℃ ~ 85℃ (TJ)
Package / Case
Supplier Device Package