$0 - $0 | 1 Pieces(Min. Order)
For product pricing customization or other inquiries
FPGAKey Technical Documents
Download Datasheet
The XC73108-20PC84C family employs a unique Dual-Block architecture, which provides high speed operations via Fast Function Blocks and/or high density capability via High Density
Function Blocks.
Fast Function Blocks (FFBs) provide fast, pin-to-pin speed and logic throughput for critical decoding and ultrafast state machine applications. High-Density Function Blocks (FBs) provide maximum logic density and systemlevel features to implement complex functions with predictable timing for adders and accumulators, wide functions and state machines requiring large numbers of
product terms, and other forms of complex logic.
In addition, the XC73108-20PC84C architecture employs the Universal Interconnect Matrix (UIM) which guarantees 100% interconnect of all internal functions. This interconnect
scheme provides constant, short interconnect delays for all routing paths through the UIM. Constant interconnect delays simplify device timing and guarantee design performance, regardless of logic placement within the chip.All XC73108-20PC84C devices are designed in 0.8µ CMOS EPROM technology.
All XC73108-20PC84C EPLDs include programmable power management features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while non-critical paths dissipate less power.
Xilinx development software supports XC73108-20PC84C EPLD design using third-party schematic entry tools, HDL compilers, or direct equation-based text files. Using a PC or a workstation and one of these design capture methods, designs are automatically mapped to an XC73108-20PC84C EPLD in a matter of minutes.
The XC73108-20PC84C devices are available in plastic and ceramic leaded chip carriers, pin-grid-array (PGA), ball-grid-array (BGA), and quad flat pack (QFP) packages. Package options include both windowed ceramic for design prototypes and one-time programmable plastic versions for cost-effective production volume.
• High-performance Erasable Programmable Logic Devices (EPLDs)
– 5 / 7.5 ns pin-to-pin speeds on all fast inputs
– Up to 167 MHz maximum clock frequency
• Advanced Dual-Block architecture
– Fast Function Blocks
– High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144)
• 100% interconnect matrix
• High-speed arithmetic carry network
– 1 ns ripple-carry delay per bit
– 43 to 61 MHz 18-bit accumulators
• Multiple independent clocks
• Each input programmable as direct, latched, or registered
• High-drive 24 mA output
• I/O operation at 3.3 V or 5 V
• Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
• Power management options
• Multiple security bits for design protection
• Supported by industry standard design and verification tools
• 100% PCI compliant
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
| Specification | Value |
|---|---|
| Typical 22V10 Equivalent | 12 |
| Number of Macrocells | 108 |
| Number of Function Blocks | 12 |
| Number of Flip-Flops | 198 |
| Number of Fast Inputs | 12 |
| Number of Signal Pins | 120 |
Support