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Download DatasheetThe XC6VLX760-3FFG1760I FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Xilinx XC6VLX760-3FFG1760I contain many builtin system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGAbased systems. Built on a 40 nm state-of-the-art copper process technology, XC6VLX760-3FFG1760I FPGAs are a programmable alternative to custom ASIC technology. offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.
Compatibility across sub-families
LXT and SXT devices are footprint compatible in the same package
Advanced, high-performance FPGA Logic
Real 6-input look-up table (LUT) technology
Dual LUT5 (5-input LUT) option
LUT/dual flip-flop pair for applications requiring rich register mix
Improved routing efficiency
64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT
SRL32/dual SRL16 with registered outputs option
Powerful mixed-mode clock managers (MMCM)
MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, inputjitter filtering, and phase-matched clock division
High-performance parallel SelectIO technology
1.2 to 2.5V I/O operation
Source-synchronous interfacing using ChipSync technology
Digitally controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support with integrated write-leveling capability
Advanced DSP48E1 slices
Flexible configuration options
Integrated interface blocks for PCI Express designs
Compliant to the PCI Express Base Specification 2.0
Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with GTX transceivers
Endpoint and Root Port capable
X1, x2, x4, or x8 lane support per block
GTX transceivers: up to 6.6 Gb/s
Data rates below 480 Mb/s supported by oversampling in FPGA logic.
GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s
Integrated 10/100/1000 Mb/s Ethernet MAC block
40 nm copper CMOS process technology
1.0V core voltage (-1, -2, -3 speed grades only)
Lower-power 0.9V core voltage option (-1L speed grade only)
High signal-integrity flip-chip packaging available in standard or Pb-free package options
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
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