XC4005A-6PQG208C of Xilinx XC4000 Logic Cell Array Families

XC4005A-6PQG208C FPGAs Overview

The XC4005A-6PQG208C of FPGAs offers four devices at the low end of the XC4000 family complexity range. XC4000A differs from XC4000 in four areas: fewer routing resources, fewer wide-edge decoders, higher output sink current, and improved output slew-rate control.

• The XC4005A-6PQG208C routing structure is optimized for smaller designs, naturally requiring fewer routing resources. The XC4000A devices have four Longlines and four singlelength lines per row and column, while the XC4005A devices have six Longlines and eight single-length lines per row and column. This results in a smaller chip area and lower cost per device.

• XC4005A-6PQG208C has two wide-edge decoders on every device edge, while the XC4000 has four. All other wide-decoder features are identical in XC4000 and XC4000A.

• XC4005A-6PQG208C outputs are specified at 24 mA, sink current, while XC4000 outputs are specified at 12 mA. The source current is the same 4 mA for both families.

• The XC4005A-6PQG208C offers a more sophisticated output slew-rate control structure with four configurable options for each individual output driver: fast, medium fast, medium slow, and slow. Slew-rate control can alleviate ground-bounce problems when multiple outputs switch simultaneously, and it can reduce or eliminate crosstalk and transmission-line effects on printed circuit boards.

Features

• Third Generation Field-Programmable Gate Arrays
– Abundant flip-flops
– Flexible function generators
– On-chip ultra-fast RAM
– Dedicated high-speed carry-propagation circuit
– Wide edge decoders (two per edge)
– Hierarchy of interconnect lines
– Internal 3-state bus capability
– Eight global low-skew clock or signal distribution
network
• Flexible Array Architecture
– Programmable logic blocks and I/O blocks
– Programmable interconnects and wide decoders
• Sub-micron CMOS Process
– High-speed logic and Interconnect
– Low power consumption
• Systems-Oriented Features
– IEEE 1149.1-compatible boundary-scan logic support
– Programmable output slew rate (4 modes)
– Programmable input pull-up or pull-down resistors
– 24-mA sink current per output (48 per pair)
• Configured by Loading Binary File
– Unlimited reprogrammability
– Six programming modes
• XACT Development System runs on ’386/’486-type PC, NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series
– Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD
– Fully automatic partitioning, placement and routing
– Interactive design editor for design optimization
– 288 macros, 34 hard macros, RAM/ROM compiler

FAQ

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