XC3SD3400A-4FGG676C

Features

• Very low cost, high-performance DSP solution for high-volume, cost-conscious applications
• 250 MHz XtremeDSP DSP48A Slices
• Dedicated 18-bit by 18-bit multiplier
• Available pipeline stages for enhanced performance of at least 250 MHz in the standard -4 speed grade
• 48-bit accumulator for multiply-accumulate (MAC) operation
• Integrated adder for complex multiply or multiply-add operation
• Integrated 18-bit pre-adder
• Optional cascaded Multiply or MAC
• Hierarchical SelectRAM memory architecture
• Up to 2268 Kbits of fast block RAM with byte write enables for processor applications
• Up to 373 Kbits of efficient distributed RAM
• Registered outputs on the block RAM with operation of at least 280 MHz in the standard -4 speed grade
• Dual-range VCCAUX supply simplifies 3.3V-only design
• Suspend, Hibernate modes reduce system power
• Low-power option reduces quiescent current
• Multi-voltage, multi-standard SelectIO interface pins
• Up to 519 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Selectable output drive, up to 24 mA per pin
• QUIETIO standard reduces I/O switching noise
• Full 3.3V ± 10% compatibility and hot swap compliance
• 622+ Mb/s data transfer rate per differential I/O
• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors
• Enhanced Double Data Rate (DDR) support
• DDR/DDR2 SDRAM support up to 333 Mb/s
• Fully compliant 32-/64-bit, 33/66 MHz PCI support
• Abundant, flexible logic resources
• Densities up to 53712 logic cells, including optional shift register
• Efficient wide multiplexers, wide logic, fast carry logic
• IEEE 1149.1/1532 JTAG programming/debug port
• Eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 320 MHz)
• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 BPI parallel NOR Flash PROM
• Low-cost Xilinx Platform Flash with JTAG
• Unique Device DNA identifier for design authentication
• Load multiple bitstreams under FPGA control
• Post-configuration CRC checking
• MicroBlaze and PicoBlaze embedded processor cores
• BGA and CSP packaging with Pb-free options
• Common footprints support easy density migration
• XA Automotive version available

FAQ

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• Q: How can I obtain software development tools related to the Xilinx FPGA platform?
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