The XC3S1200E-4FGG400C Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Datasheet.
The XC3S1200E-4FGG400C ncreasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions.These XC3S1200E-4FGG400C FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.
Because of their exceptionally low cost, XC3S1200E-4FGG400C FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.
The XC3S1200E-4FGG400C is a superior alternative to mask programmed ASICs. avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, XC3S1200E-4FGG400C FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.The Xilinx Embedded - FPGAs (Field Programmable Gate Array) series XC3S1200E-4FGG400C is FPGA Spartan-3E Family 1.2M Gates 19512 Cells 572MHz 90nm (CMOS) Technology 1.2V , View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
• SelectIO signaling
- Up to 633 I/O pins
- Eighteen single-ended signal standards
- Eight differential signal standards including LVDS
- Double Data Rate (DDR) support
• Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
• SelectRAM hierarchical memory
- Up to 1,728 Kbits of total block RAM
- Up to 432 Kbits of total distributed RAM
• Digital Clock Manager (four DCMs)
- Clock skew elimination
- Frequency synthesis
- High-resolution phase shifting
Internet of Things
Number of LABs/CLBs
Number of Logic Elements/Cells
Total RAM Bits
Number of I/O
Number of Gates
Voltage - Supply
1.14V ~ 1.26V
0℃ ~ 85℃ (TJ)
Package / Case
Supplier Device Package