$11.315 - $33 | 1 Pieces(Min. Order)
For product pricing customization or other inquiries
Contact NowFPGAKey Technical Documents
Download DatasheetXC3142A provides a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program.
The FPGA's XC3142A-4PG132C user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable package.
• Ultra-high-speed FPGA family with six members
- 50-85 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
• High-end additional family member in the 22 X 22 CLB array-size XC3195A device
• 8 mA output sink current and 8 mA source current
• Maximum power-down and quiescent current is 5 mA
• 100% architecture and pin-out compatible with other XC3000 families
• Software and bitstream compatible with the XC3000, XC3000A, and XC3000L families
XC3100A combines the features of the XC3000A and XC3100 families:
• Additional interconnect resources for TBUFs and CE inputs
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during initial power-up
• More advanced CMOS process
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
11+ $32.8836
20+ $32.3928
30+ $31.9020
60+ $31.4112
110+ $30.9204
14+ $23.3728
20+ $23.0076
30+ $22.8250
70+ $22.6424
140+ $22.4598
11+ $33.0145
20+ $32.9818
30+ $32.9490
60+ $32.9163
110+ $32.8836
14+ $23.3728
20+ $23.0076
30+ $22.8250
70+ $22.6424
140+ $22.4598
11+ $32.8836
20+ $32.3928
30+ $31.9020
60+ $31.4112
110+ $30.9204
14+ $23.3728
20+ $23.0076
30+ $22.8250
70+ $22.6424
140+ $22.4598
14+ $24.4684
20+ $24.1032
30+ $23.7380
70+ $23.3728
140+ $23.0076
28+ $12.0332
30+ $11.8536
60+ $11.6740
140+ $11.4944
280+ $11.3148
Support