$7.306 - $11.029 | 1 Pieces(Min. Order)
For product pricing customization or other inquiries
FPGAKey Technical Documents
Download Datasheet- Fully automatic mapping, placement, and routing
General Overview
The Spartan-II family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs).
There are four Delay-Locked Loops (DLLs), one at each corner of the die.
Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns.
These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1).
Spartan-II FPGAs are customized by loading configuration data into internal static memory cells.
Unlimited reprogramming cycles are possible with this approach.
Stored values in these cells determine logic functions and interconnections implemented in the FPGA.
Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes.
Spartan-II FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits.
Spartan-II FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology.
Spartan-II devices provide system clock rates up to 200 MHz.
In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-II FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features.
• Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Core logic powered at 2.5V and I/Os powered at 1.5V, 2.5V, or 3.3V
• Fully supported by powerful Xilinx ISE development system
- Fully automatic mapping, placement, and routing
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
| Specification | Value |
|---|---|
| Number of LABs/CLBs | 216 |
| Number of Logic Elements/Cells | 972 |
| Total RAM Bits | 24576 |
| Number of I/O | 92 |
| Number of Gates | 30000 |
| Voltage - Supply | 2.375V ~ 2.625V |
| Mounting Type | Surface Mount |
| Operating Temperature | 0℃ ~ 85℃ (TJ) |
| Package / Case | 144-TFBGA, CSPBGA |
| Supplier Device Package | 144-LCSBGA (12x12) |
FPGA Spartan-II Family 30K Gates 972 Cells 263MHz 0.18um Technology 2.5V 100-Pin VTQFP
FPGA Spartan-II Family 30K Gates 972 Cells 263MHz 0.18um Technology 2.5V 100-Pin VTQFP
SPARTAN-II Field-Programmable Gate Array
FPGA Spartan-II Family 30K Gates 972 Cells 263MHz 0.18um Technology 2.5V 144-Pin CSBGA
198+ $61.9663
396+ $57.476
792+ $48.4953
1188+ $44.005
1584+ $39.874
1980+ $35.0244
19800+ $32.8691
198+ $27.4165
1+ $28.0600
Support