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Home > FPGA Familis > CoolRunner-II CPLD > XC2C512-7FT256I

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$31.235 - $73.529 | 1 Pieces(Min. Order)

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CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
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XC2C512-7FT256I FPGAs Overview

The XC2C512-7FT256I of CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This XC2C512-7FT256I device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds.

A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the XC2C512-7FT256I device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.

The Xilinx CPLDs series XC2C512-7FT256I is CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um (CMOS) Technology 1.8V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


• Optimized for 1.8V systems
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pullup on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable


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  • Q: How can I obtain software development tools related to the Xilinx FPGA platform?
  • In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Xilinx XC2C512 Development Boards, Evaluation Boards, or CoolRunner-II CPLD Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain XC2C512-7FT256I technical support documents?
  • Enter the "XC2C512-7FT256I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for XC2C5127FT256I in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the XC2C512-7FT256I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Programmable Type
    In System Programmable
  • Delay Time tpd(1) Max
  • Voltage Supply - Internal
    1.7V ~ 1.9V
  • Number of Logic Elements/Blocks
  • Number of Macrocells
  • Number of Gates
  • Number of I/O
  • Operating Temperature
    -40℃ ~ 85℃ (TA)
  • Mounting Type
    Surface Mount
  • Package / Case
  • Supplier Device Package
    256-FTBGA (17x17)

Technical Documents

  • XC2C512 Technical Support PDF Datasheet Overview Download>>

Circuit Diagram

XC2C512-7FT256I PDF Preview

XC2C512-7FT256I Tags

  • Xilinx XC2C512
  • XC2C512 development board
  • CoolRunner-II CPLD evaluation kit
  • Xilinx CoolRunner-II CPLD development board
  • CoolRunner-II CPLD starter kit
  • CoolRunner-II CPLD XC2C512
  • XC2C512 reference design
  • XC2C512 evaluation board
  • XC2C512-7FT256I Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • BUY
  • avnet
  • XC2C512-7FT256I
  • Xilinx
  • CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA (Alt: XC2C512-7FT256I)RoHS: Not Compliant
  • 87
  • 90+ $324.1171
    180+ $300.6304
    360+ $253.6569
    540+ $230.1701
    720+ $208.5623
    900+ $183.1966
    9000+ $171.923

  • digikey
  • XC2C512-7FT256I
  • IC CPLD 512MC 7.1NS 256BGA
  • 0
  • 1+ $122.2900

  • mouser
  • XC2C512-7FT256I
  • Xilinx
  • CPLD - Complex Programmable Logic Devices XC2C512-7FT256I
  • 80
  • 1+ $150.0000
    25+ $146.7500

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