This XC2C32A-6QFG32C device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.
Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.
The XC2C32A-6QFG32C CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This XC2C32A-6QFG32C device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs.
By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II 128 macrocell XC2C32A-6QFG32C device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.The Xilinx CPLDs series XC2C32A-6QFG32C is CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 200MHz 0.18um (CMOS) Technology 1.8V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
• In-System Programmable PROMs for Configuration of Xilinx FPGAs
• Low-Power Advanced CMOS NOR Flash Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range (–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA Configuration
Internet of Things
In System Programmable
Delay Time tpd(1) Max
Voltage Supply - Internal
1.7V ~ 1.9V
Number of Logic Elements/Blocks
Number of Macrocells
Number of Gates
Number of I/O
0℃ ~ 70℃ (TA)
Package / Case
32-VFQFN Exposed Pad
Supplier Device Package