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Home > FPGA Familis > CoolRunner-II CPLD > XC2C256-FTG256CMS
XC2C256-FTG256CMS

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XC2C256-FTG256CMS

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$22.35 - $232 | 1 Pieces(Min. Order)

Manufacturer:
Xilinx
Package/Case:
BGA
RoHS:
-
Lifecycle:
-
Stock Resource:
Factory Excess Stock / Franchised Distributor
Product Categories:
CoolRunner-II CPLD
Description:
CoolRunner-II CPLD Family
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XC2C256-FTG256CMS FPGAs Overview

The CoolRunner-II 128 macrocell CPLD is I/O compatible with various JEDEC I/O standards (see Table 1). This XC2C256-FTG256CMS device is also 1.5V I/O compatible with the use of Schmitt-trigger inputs. The XC2C256-FTG256CMS device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved

This XC2C256-FTG256CMS device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis.

A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the XC2C256-FTG256CMS device.

Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature

DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.

By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.

Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the XC2C256-FTG256CMS device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

Features

• Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis. Refer to the CoolRunner-II family data sheet for architecture description.
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- 132-ball CP (0.5mm) BGA with 106 user I/O
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 184 user I/O
- Pb-free available for all packages

FAQ

  • Q: Does the price of XC2C256-FTG256CMS devices fluctuate frequently?
  • The FPGAkey search engine monitors the XC2C256-FTG256CMS inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for XC2C256-FTG256CMS?
  • No, only submit the quantity, email address and other contact information required for the inquiry of XC2C256-FTG256CMS, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Xilinx FPGA platform?
  • In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Xilinx XC2C256 Development Boards, Evaluation Boards, or CoolRunner-II CPLD Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain XC2C256-FTG256CMS technical support documents?
  • Enter the "XC2C256-FTG256CMS" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for XC2C256FTG256CMS in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the XC2C256-FTG256CMS pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Documents

  • XC2C256 Technical Support PDF Datasheet Overview Download>>

XC2C256-FTG256CMS PDF Preview

XC2C256-FTG256CMS Tags

  • Xilinx XC2C256
  • XC2C256 development board
  • CoolRunner-II CPLD evaluation kit
  • Xilinx CoolRunner-II CPLD development board
  • CoolRunner-II CPLD starter kit
  • CoolRunner-II CPLD XC2C256
  • XC2C256 reference design
  • XC2C256 evaluation board
  • XC2C256-FTG256CMS Datasheet PDF

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  • avnet
  • XC2C256-10FT256C
  • Xilinx
  • CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA (Alt: XC2C512-10FT256C)RoHS: Not Compliant
  • 0
  • 90+ $191.589
    180+ $177.7058
    360+ $149.9392
    540+ $136.056
    720+ $123.2834
    900+ $108.2895
    9000+ $101.6255

  • avnet
  • XC2C256-10FT256I
  • Xilinx
  • CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA (Alt: XC2C512-10FT256I)RoHS: Not Compliant
  • 0
  • 90+ $231.5385
    180+ $214.7603
    360+ $181.204
    540+ $164.4259
    720+ $148.99
    900+ $130.8696
    9000+ $122.8161

  • avnet
  • XC2C256-10FTG256C
  • Xilinx
  • CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 256MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA (Alt: XC2C256-6FTG256C)
  • 0
  • 90+ $87.1363
    180+ $80.8221
    360+ $68.1936
    540+ $61.8794
    720+ $56.0703
    900+ $49.2509
    9000+ $46.2201

  • avnet
  • XC2C256-10FTG256I
  • Xilinx
  • CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 256-Pin FTBGA (Alt: XC2C256-7FTG256I)
  • 41
  • 90+ $75.3243
    180+ $69.866
    360+ $58.9494
    540+ $53.4912
    720+ $48.4695
    900+ $42.5746
    9000+ $39.9546

  • avnet
  • XC2C256-10TQG144C
  • Xilinx
  • CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 144-Pin TQFP (Alt: XC2C256-7TQG144C)
  • 0
  • 60+ $24.2794
    120+ $23.9578
    240+ $23.6363
    360+ $23.3147
    480+ $22.9931
    600+ $22.6715
    6000+ $22.3499

  • digikey
  • XC2C256-10FTG256C
  • Xilinx
  • IC CPLD 256MC 5.7NS 256FTBGA
  • 0
  • 90+ $39.1949

  • digikey
  • XC2C256-10FTG256I
  • Xilinx
  • IC CPLD 256MC 6.7NS 256FTBGA
  • 1117
  • 1+ $35.0263
    25+ $33.5776
    100+ $33.3267

  • digikey
  • XC2C256-10TQG144C
  • Xilinx
  • IC CPLD 256MC 6.7NS 144QFP
  • 0
  • 1+ $25.7864
    25+ $24.7002
    100+ $24.5435

  • element14
  • XC2C256-10TQG144C
  • Xilinx
  • , CPLD, 6.7NS, 152MHZ, TQFP-144RoHS: Compliant Min Qty: 1 Container: Each
  • 0
  • 1+ $23.3814
    25+ $22.9218
    100+ $22.9111

  • mouser
  • XC2C256-10FT256C
  • Xilinx
  • CPLD - Complex Programmable Logic Devices XC2C512-10FT256C
  • 3
  • 1+ $89.1600
    25+ $87.3600

  • mouser
  • XC2C256-10FT256I
  • Xilinx
  • CPLD - Complex Programmable Logic Devices XC2C512-10FT256I
  • 143
  • 1+ $106.9800
    25+ $104.8400

  • mouser
  • XC2C256-10FTG256C
  • Xilinx
  • CPLD - Complex Programmable Logic Devices XC2C256-6FTG256CRoHS: Compliant
  • 232
  • 1+ $40.5600
    25+ $39.7400
    90+ $39.7200

  • mouser
  • XC2C256-10FTG256I
  • Xilinx
  • CPLD - Complex Programmable Logic Devices XC2C256-7FTG256IRoHS: Compliant
  • 150
  • 1+ $34.8000
    25+ $34.1100
    90+ $34.0900

  • newark
  • XC2C256-10FTG256I
  • Xilinx
  • No. of I/O s:184I/O s, Logic Case Style:FTBGA, Frequency:152MHz RoHS Compliant: Yes Min Qty: 90 Container: Bulk
  • 0
  • 1+ $28.4200

  • newark
  • XC2C256-10TQG144C
  • Xilinx
  • CPLD, 6.7NS, 152MHZ, TQFP-144, CPLD Type:-, No. of Macrocells:256, No. of I/O s:118I/O s, Logic Case Style:TQFP, No. of Pins:144Pins, Frequency:152MHz, Supply Voltage Min:1.7V, Supply Voltage Max:1.9V, Propagation Delay:6.7ns, GlobalRoHS Compliant: Yes Min Qty: 1 Container: Bulk
  • 0
  • 1+ $25.4000

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