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FPGAKey Technical Documents
Download DatasheetThe Logic Cell Array (LCA) is a high density CMOS integrated circuit. Its XC2064-125PC68I is made up of three types of configurable elements: Input/Output Blocks, logic blocks and Interconnect. The designer can define individual l/O blocks for interface to external circuitry, define logic blocks to implement logic functions and define interconnection networks to compose larger scale logic functions. The XACT Development System provides interactive graphic design capture and auto-matic routing. Both logic simulation and in-circuit emula-tion are available for design verification.
The XC2000 family operates with a nominal 5.0 V supply.
The XC2000L family operates with nominal 3.3 V supply.
The LCA logic functions and interconnections are determined by data stored in internal static-memory cells. On-chip logic provides for automatic loading of configuration data at power-up. The program data can reside in an EEPROM, EPROM or ROM on the circuit board or on a floppy disk or hard disk. The program can be loaded in a number of modes to accommodate various system requirements.
Architecture
The general structure of a Logic Cell Array is shown in XC2064-125PC68I Diagram. The elements of the array include three catego-
ries of user programmable elements:I/O Blocks(IOBs), Configurable Logic Blocks (CLBs) and Programmable Interconnections. The I/OBs provide an interface between the logic array and the device package pins. The CLBs perform user-specified logic functions, and the interconnect resources are programmed to form networks that carry logic signals among the blocks.
LCA configuration is established through a distributed array of memory cells. The XACT development system generates the program used to configure the Logic CellArray which includes logic to implement automatic con-
figuration.
Configuratlon Memory
The XC2064-125PC68I is established by programming memory cells which determine the logic functions and interconnections. The memory loading process is independent of the user logic functions.
· Fully Field-Programmable:
-I/O functions
-Digital logic functions
-Interconnections
· General-purpose array architecture
· Complete user control of design cycle
· Compatible arrays with logic cell complexity equivalent from 600 to 1,500 gates
· Available in 5-V and 3.3-V versions
·100% factory tested
· Selectable configuration modes
· Low-power, CMOS, static-memory technology
· Performance equivalent to TTL SSI/MSI
· TTL or CMOS input thresholds
· Complete development system support
-XACT Design Editor
-Schematic Entry
-Macro Library
-Timing Calculator
-Logic and Timing Simulator
-Auto Place/Route
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