XC18V512-VQ44C of Xilinx Memory - Configuration Proms for FPGA's

XC18V512-VQ44C FPGAs Overview

The Xilinx XC18V512-VQ44C Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.

When the XC18V512-VQ44C FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin.

When the XC18V512-VQ44C FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.

Features

In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs

Endurance of 20,000 Program/Erase Cycles
Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)

IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA Configuration
Simple Interface to the FPGA
Cascadable for Storing Longer or Multiple Bitstreams
Low-Power Advanced CMOS FLASH Process
Dual Configuration Modes

Serial Slow/Fast Configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)

5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
Design Support Using the Xilinx ISE Foundation Software Packages
Available in PC20, SO20, PC44, and VQ44 Packages
Lead-Free (Pb-Free) Packaging

FAQ

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