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FPGAKey Technical Documents
Download DatasheetThe Xilinx XC18V04VQG44I provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. XC18V04VQG44I devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.
In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
Endurance of 20,000 Program/Erase Cycles
Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA Configuration
Simple Interface to the FPGA
Cascadable for Storing Longer or Multiple Bitstreams
Low-Power Advanced CMOS FLASH Process
Dual Configuration Modes
Serial Slow/Fast Configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)
5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
Design Support Using the Xilinx ISE Foundation Software Packages
Available in PC20, SO20, PC44, and VQ44 Packages
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
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