XC18V01PCG20I of Xilinx Memory - Configuration Proms for FPGA's

XC18V01PCG20I FPGAs Overview

The Xilinx XC18V01PCG20I provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.

When theXC18V01PCG20I FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA. After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.

Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.

Features

In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs

Endurance of 20,000 Program/Erase Cycles
Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)

IEEE Std 1149.1 Boundary-Scan (JTAG) Support
JTAG Command Initiation of Standard FPGA Configuration
Simple Interface to the FPGA
Cascadable for Storing Longer or Multiple Bitstreams
Low-Power Advanced CMOS FLASH Process
Dual Configuration Modes

Serial Slow/Fast Configuration (up to 33 MHz)
Parallel (up to 264 Mb/s at 33 MHz)

5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
3.3V or 2.5V Output Capability
Design Support Using the Xilinx ISE Foundation Software Packages
Available in PC20, SO20, PC44, and VQ44 Packages
Lead-Free (Pb-Free) Packaging

FAQ

Q: Does the price of XC18V01PCG20I devices fluctuate frequently?
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Q: How can I obtain software development tools related to the Xilinx FPGA platform?
In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Xilinx XC18V01 Development Boards, Evaluation Boards, or Memory - Configuration Proms for FPGAs Starter Kit? also provide technical information?
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Q: How to obtain XC18V01PCG20I technical support documents?
Enter the "XC18V01PCG20I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for XC18V01PCG20I in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the XC18V01PCG20I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.