$11.843 - $13 | 1 Pieces(Min. Order)
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FPGAKey Technical Documents
Download DatasheetThe Xilinx XC17V01VC provide an easy-to-use, costeffective method for storing large Xilinx FPGA configuration bitstreams.
The XC17V01VC PROM can configure a Xilinx FPGA using the FPGA serial configuration mode interface. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.
One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
Low-power CMOS floating-gate process
3.3V supply voltage
Guaranteed 20 year life data retention
Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20(1)
Programming support by leading programmer manufacturers
Design support using the ISE Foundation and ISE WebPACK software
Dual configuration modes for the XC17V16 and XC17V08(1) devices
Serial slow/fast configuration (up to 20 Mb/s)
Parallel (up to 160 Mb/s at 20 MHz)
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
| Specification | Value |
|---|---|
| Configuration Bits | 1,679,360 |
26+ $13.1588
30+ $12.9624
60+ $12.7660
130+ $12.5696
260+ $12.3732
26+ $13.1588
30+ $12.9624
60+ $12.7660
130+ $12.5696
260+ $12.3732
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