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Download DatasheetThe XC1765EPI provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. After configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.
One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGAs
Simple interface to the FPGA; requires only one user I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L series support fast configuration
Low-power CMOS floating-gate process
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
Available in compact plastic packages: 8-pin SOIC, 8- pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44- pin PLCC or 44-pin VQFP
Programming support by leading programmer manufacturers
Design support using the Xilinx Alliance and Foundation software packages
Guaranteed 20 year life data retention
Lead-free (Pb-free) packaging available
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
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