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Download DatasheetFPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor.
The Xilinx Memory - Configuration Proms for FPGA's series XC1736EPD8I is Configuration PROMs, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.Artificial Intelligence
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Specification | Value |
---|---|
Programmable Type | OTP |
Memory Size | 36kb |
Voltage - Supply | 4.5V ~ 5.5V |
Operating Temperature | -40℃ ~ 85℃ |
Package / Case | 8-DIP (0.300, 7.62mm) |
Supplier Device Package | 8-PDIP |
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90+ $4.0920
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410+ $3.9680
810+ $3.9060
81+ $4.1540
90+ $4.0920
170+ $4.0300
410+ $3.9680
810+ $3.9060
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