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FPGAKey Technical Documents
Download DatasheetThe XC17256ELV08I provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. After configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The XC17256ELV08I inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family.
One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGAs
Simple interface to the FPGA; requires only one user I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions
Available in compact plastic packages: 8-pin SOIC, 8- pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44- pin PLCC or 44-pin VQFP
Programming support by leading programmer manufacturers
Design support using the Xilinx Alliance and Foundation software packages
Guaranteed 20 year life data retention
Lead-free (Pb-free) packaging available
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