This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Familis > XA Zynq-7000 SoC > XA7Z010-1CLG400Q

Images are for reference only.


Get Latest Price >

$64.634 - $83.194 /Piece | 1 Piece/Pieces (Min. Order)




Factory Excess Stock / Franchised Distributor

Embedded - System On Chip (SoC)

FPGA Zynq-7000 Family 430K Gates 28000 Cells 28nm Technology Automotive 400-Pin CSBGA

XA7Z010-1CLG400Q FPGAs Overview

The XA Zynq™-7000 Automotive family is based on the Xilinx® All Programmable SoC architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. This highly integrated, flexible, and power-optimized solution is ideal for high computationally intensive and performance demanding applications. The automotive family focuses on automotive applications and consists of the Z-7010, Z-7020, and Z-7030 devices.

The Xilinx Embedded - System On Chip (SoC) series XA7Z010-1CLG400Q is Microprocessor Circuit, CMOS, PBGA400, 17 X 17MM, 0.8MM PITCH, LEAD FREE, BGA-400, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


  • 2.5 DMIPS/MHz per CPU
  • CPU frequency: Up to 667 MHz
  • Coherent multiprocessor support
  • ARMv7-A architecture
    • TrustZone security
    • Thumb-2 instruction set
  • Jazelle RCT execution Environment Architecture
  • NEON media-processing engine
  • Single and double precision Vector Floating Point Unit (VFPU)
  • CoreSight™ technology and Program Trace Macrocell (PTM)
  • Timer and Interrupts
    • Three watchdog timers
    • One global timer
    • Two triple-timer counters


  • 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)
  • 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
  • Byte-parity support

On-Chip Memory

  • On-chip boot ROM
  • 256 KB on-chip RAM (OCM)
  • Byte-parity support

External Memory Interfaces

  • Multiprotocol dynamic memory controller
  • 16-bit or 32-bit interfaces to DDR3L, DDR3, DDR2, or LPDDR2 memories
  • ECC support in 16-bit mode
  • 1 GB of address space using single rank of 8-, 16-, or 32-bit-wide memories
  • Static memory interfaces
    • 8-bit SRAM data bus with up to 64 MB support
    • Parallel NOR flash support
    • ONFI1.0 NAND flash support (1-bit ECC)
    • 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash

8-Channel DMA Controller

  • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support

I/O Peripherals and Interfaces

  • Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
    • Scatter-gather DMA capability
    • Recognition of 1588 rev. 2 PTP frames
    • GMII and RGMII interfaces
  • Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints
    • USB 2.0 compliant device IP core
    • On-the-go, high-speed, full-speed, and low-speed modes support
    • Intel EHCI compliant USB host
    • 8-bit ULPI external PHY interface
  • Two full CAN 2.0B compliant CAN bus interfaces
    • CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant
    • External PHY interface
  • Two SD/SDIO 2.0/MMC3.31 compliant controllers
  • Two full-duplex SPI ports with three peripheral chip selects
  • Two high-speed UARTs (up to 1 Mb/s)
  • Two master and slave I2C interfaces
  • GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up to two banks of 32b) connected to the programmable logic (PL)
  • Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments


  • High-bandwidth connectivity within PS and between PS and PL
  • ARM AMBA AXI based
  • QoS support on critical masters for latency and bandwidth control

Programmable Logic (PL)

Configurable Logic Blocks (CLB)

  • Look-up tables (LUT)
  • Flip-flops
  • Cascadeable adders

36 Kb Block RAM

  • True Dual-Port
  • Up to 72 bits wide
  • Configurable as dual 18 kb

DSP Blocks

  • 18 x 25 signed multiply
  • 48-bit adder/accumulator
  • 25-bit pre-adder

Programmable I/O Blocks

  • Supports LVCMOS, LVDS, and SSTL
  • 1.2V to 3.3V I/O
  • Programmable I/O delay and SerDes

JTAG Boundary-Scan

  • IEEE Std 1149.1 Compatible Test Interface

Two 12-Bit Analog-to-Digital Converters

  • On-chip voltage and temperature sensing
  • Up to 17 external differential input channels
  • One million samples per second maximum conversion rate

Automotive Temperature Range

  • I-Grade: Tj = –40°C to +100°C
  • Q-Grade: Tj = –40°C to +125°C

Automotive Standards

  • AEC-Q100 qualification (Beyond AEC-Q100 Qualification is available upon request)
  • Production Part Approval Process (PPAP) Documentation

Serial Transceivers

  • Up to 4 receivers and transmitters
  • Supports up to 6.6 Gb/s data rates

PCI Express® Block

  • Root Complex and Endpoint configurations
  • Supports up to Gen2 speeds
  • Supports up to 4 lanes


  • Q: Does the price of XA7Z010-1CLG400Q devices fluctuate frequently?
  • The FPGAkey search engine monitors the XA7Z010-1CLG400Q inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for XA7Z010-1CLG400Q?
  • No, only submit the quantity, email address and other contact information required for the inquiry of XA7Z010-1CLG400Q, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the Xilinx FPGA platform?
  • In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Xilinx XA7Z010 Development Boards, Evaluation Boards, or XA Zynq-7000 SoC Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain XA7Z010-1CLG400Q technical support documents?
  • Enter the "XA7Z010-1CLG400Q" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for XA7Z0101CLG400Q in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the XA7Z010-1CLG400Q pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Architecture


  • Core Processor

    Dual ARM? Cortex?-A9 MPCore? with CoreSight?

  • RAM Size


  • Peripherals


  • Connectivity


  • Speed


  • Primary Attributes

    Artix?-7 FPGA, 28K Logic Cells

  • Operating Temperature

    -40℃ ~ 125℃ (TJ)

  • Package / Case


  • Supplier Device Package

    400-CSPBGA (17x17)

Technical Documents

  • XA Zynq-7000 SoC Data Sheet: Overview Download>>

XA7Z010-1CLG400Q PDF Preview

XA7Z010-1CLG400Q Tags

  • Xilinx XA7Z010
  • XA7Z010 development board
  • XA Zynq-7000 SoC evaluation kit
  • Xilinx XA Zynq-7000 SoC development board
  • XA Zynq-7000 SoC starter kit
  • XA Zynq-7000 SoC XA7Z010
  • XA7Z010 reference design
  • XA7Z010 evaluation board
  • XA7Z010-1CLG400Q Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • BUY
  • avnet
  • XA7Z010-1CLG400Q
  • Xilinx
  • 0
  • 1+ $84.4817
    10+ $81.9371
    30+ $77.8657
    50+ $75.8300
    100+ $72.2675
    250+ $67.6872
    500+ $64.6336

  • avnet
  • XA7Z010-1CLG400Q4715
  • Xilinx
  • 0
  • 90+ $81.0000
    180+ $80.0000
    270+ $79.0244
    450+ $78.0723
    900+ $77.1429
    2250+ $75.3488
    4500+ $73.6364

  • avnet
  • XA7Z010-1CLG400Q4835
  • Xilinx
  • 0
  • 750+ $22.6250
    1500+ $22.3457
    2250+ $22.0732
    3750+ $21.8072
    7500+ $21.5476
    18750+ $21.0465
    37500+ $20.5682

  • avnet
  • XA7Z010-1CLG400Q4954
  • Xilinx
  • 0
  • 90+ $73.6250
    180+ $72.7160
    270+ $71.8293
    450+ $70.9639
    900+ $70.1191
    2250+ $68.4884
    4500+ $66.9318

  • digikey
  • XA7Z010-1CLG400Q
  • 0
  • 5+ $83.1939

Need Help?


If you have any questions about the product and related issues, Please contact us.