$25.55 - $25.735 | 1 Pieces(Min. Order)
For product pricing customization or other inquiries
FPGAKey Technical Documents
Download DatasheetThe XA2C256-7VQG100C device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as “direct input” registers to store signals directly from input pins.
Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the XA2C256. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.
• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
• Guaranteed to meet full electrical specifications over
TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis.
Refer to the CoolRunner-II family data sheet for architecture description.
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- Pb-free only for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2, 4, 6, 8, 10, 12, 14, 16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pull-up on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
- Hot pluggable
WARNING: Programming temperature range of TA = 0°C to +70°C.
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V Automotive 144-Pin TQFP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V Automotive 100-Pin VTQFP
CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V Automotive 100-Pin VTQFP
60+ $66.9582
120+ $62.1061
240+ $52.402
360+ $47.55
480+ $43.0861
600+ $37.8459
6000+ $35.5169
90+ $60.721
180+ $56.3209
360+ $47.5208
540+ $43.1207
720+ $39.0727
900+ $34.3206
9000+ $32.2085
90+ $60.9769
180+ $56.5583
360+ $47.721
540+ $43.3024
720+ $39.2373
900+ $34.4652
9000+ $32.3443
60+ $73.9293
120+ $68.5721
240+ $57.8577
360+ $52.5005
480+ $47.5719
600+ $41.7861
6000+ $39.2147
90+ $66.9582
180+ $62.1061
360+ $52.402
540+ $47.55
720+ $43.0861
900+ $37.8459
9000+ $35.5169
60+ $30.1353
90+ $27.2366
90+ $27.2371
60+ $33.2153
1+ $31.3200
25+ $30.6600
120+ $30.6400
1+ $28.3200
25+ $27.8100
90+ $27.7900
1+ $28.3200
25+ $27.8100
90+ $27.7900
1+ $34.5600
25+ $33.8600
120+ $33.8400
1+ $28.2100
1+ $25.5500
Support