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Home > FPGA Familis > CoolRunner-II Automotive CPLD > XA2C256-7TQG144I

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$20.027 - $30.716 | 1 Pieces(Min. Order)

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CPLD CoolRunner -II Family 6K Gates 256 Macro Cells 152MHz 0.18um Technology 1.8V Automotive 144-Pin TQFP

XA2C256-7TQG144I FPGAs Overview

The XA2C256-7TQG144I device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as “direct input” registers to store signals directly from input pins.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the XA2C256. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.

The Xilinx CPLDs series XA2C256-7TQG144I is XA2C256-7TQG144I - NEW PRODUCT, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


• AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
• Guaranteed to meet full electrical specifications over
TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis.
Refer to the CoolRunner-II family data sheet for architecture description.
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- Pb-free only for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2, 4, 6, 8, 10, 12, 14, 16)
- Global signal options with macrocell control
· Multiple global clocks with phase selection per macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Open-drain output option for Wired-OR and LED drive
- Optional bus-hold, 3-state or weak pull-up on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
- Hot pluggable
WARNING: Programming temperature range of TA = 0°C to +70°C.


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  • Q: How can I obtain software development tools related to the Xilinx FPGA platform?
  • In FPGA/CPLD design tools, Xilinx's Vivado Design Suite is easy to use, it is very user-friendly in synthesis and implementation, and it is easier to use than ISE design tools; The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase Xilinx XA2C256 Development Boards, Evaluation Boards, or CoolRunner-II Automotive CPLD Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain XA2C256-7TQG144I technical support documents?
  • Enter the "XA2C256-7TQG144I" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for XA2C2567TQG144I in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the XA2C256-7TQG144I pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

XA2C256-7TQG144I Specifications

Specification Value
Programmable Type In System Programmable
Delay Time tpd(1) Max 7.0ns
Voltage Supply - Internal 1.7V ~ 1.9V
Number of Logic Elements/Blocks 16
Number of Macrocells 256
Number of Gates 6000
Number of I/O 118
Operating Temperature -40℃ ~ 85℃ (TA)
Mounting Type Surface Mount
Package / Case 144-LQFP
Supplier Device Package 144-TQFP (20x20)

Technical Documents

  • XA2C256 Technical Support PDF Datasheet Overview Download>>

XA2C256-7TQG144I PDF Preview

XA2C256-7TQG144I Tags

  • Xilinx XA2C256
  • XA2C256 development board
  • CoolRunner-II Automotive CPLD evaluation kit
  • Xilinx CoolRunner-II Automotive CPLD development board
  • CoolRunner-II Automotive CPLD starter kit
  • CoolRunner-II Automotive CPLD XA2C256
  • XA2C256 reference design
  • XA2C256 evaluation board
  • XA2C256-7TQG144I Datasheet PDF

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  • IC CPLD 256MC 7NS 144TQFP
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  • mouser
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  • Xilinx
  • CPLD - Complex Programmable Logic Devices XA2C256-7TQG144IRoHS: Compliant
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