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Download DatasheetThe XA2C128-8VQG100Q device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This XA2C128-8VQG100Q device consists of eight Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.
The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the XA2C128-8VQG100Q device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.
The Xilinx CPLDs series XA2C128-8VQG100Q is CPLD CoolRunner -II Family 3K Gates 128 Macro Cells 152MHz 0.18um (CMOS) Technology 1.8V 100Pin VTQFP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products. • AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade
• Guaranteed to meet full electrical specifications over TA = –40°C to +105°C with TJ Maximum = +125°C (Q-grade)
• Optimized for 1.8V systems
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in the following package options
- 100-pin VQFP with 80 user I/O
- 132-ball CP (0.5 mm) BGA with 100 user I/O
- Pb-free only for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Two separate I/O banks
· Global set/reset
- Advanced design security
- Open-drain output option for Wired-OR and LED drive
- PLA architecture
· Superior pinout retention
· 100% product term routability across function block
- Optional bus-hold, 3-state or weak pull-up on selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels
- Hot pluggable
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
Specification | Value |
---|---|
Programmable Type | In System Programmable |
Delay Time tpd(1) Max | 7.0ns |
Voltage Supply - Internal | 1.7V ~ 1.9V |
Number of Logic Elements/Blocks | 8 |
Number of Macrocells | 128 |
Number of Gates | 3000 |
Number of I/O | 80 |
Operating Temperature | -40℃ ~ 105℃ (TA) |
Mounting Type | Surface Mount |
Package / Case | 100-TQFP |
Supplier Device Package | 100-VQFP (14x14) |
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