The XC7300 family employs a unique Dual-Block architecture, which provides high speed operations via Fast Function Blocks and/or high density capability via High Density
Fast Function Blocks (FFBs) provide fast, pin-to-pin speed and logic throughput for critical decoding and ultrafast state machine applications. High-Density Function Blocks (FBs) provide maximum logic density and systemlevel features to implement complex functions with predictable timing for adders and accumulators, wide functions and state machines requiring large numbers of
product terms, and other forms of complex logic.
In addition, the XC7300 architecture employs the Universal Interconnect Matrix (UIM) which guarantees 100% interconnect of all internal functions. This interconnect
scheme provides constant, short interconnect delays for all routing paths through the UIM. Constant interconnect delays simplify device timing and guarantee design performance, regardless of logic placement within the chip.All XC7300 devices are designed in 0.8µ CMOS EPROM technology.
All XC7300 EPLDs include programmable power management features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while non-critical paths dissipate less power.
Xilinx development software supports XC7300 EPLD
design using third-party schematic entry tools, HDL compilers, or direct equation-based text files. Using a PC or a workstation and one of these design capture methods, designs are automatically mapped to an XC7300 EPLD in a matter of minutes.
The XC7300 devices are available in plastic and ceramic leaded chip carriers, pin-grid-array (PGA), ball-grid-array (BGA), and quad flat pack (QFP) packages. Package options include both windowed ceramic for design prototypes and one-time programmable plastic versions for cost-effective production volume.