Virtex UltraScale+ devices provide the highest performance and integration capabilities in a 14nm/16nm FinFET node. Xilinx 3rd generation 3D ICs use stacked silicon interconnect (SSI) technology to break through the limitations of Moore’s law and deliver the highest signal processing and serial I/O bandwidth to satisfy the most demanding design requirements. It also provides registered inter-die routing lines enabling >600 MHz operation, with abundant and flexible clocking to deliver a virtual monolithic design experience.
As the industry's most capable FPGA family, the devices are ideal for compute-intensive applications ranging from 1+Tb/s networking, and machine learning, to radar/early-warning systems.
The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory are available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal balance between the required system performance and the smallest power envelope.
3D IC-enabled FinFETs for breakthrough density, bandwidth, and massive die-to-die connections enabling virtual monolithic design
Up to 38 TOPs (22 TeraMACs) of DSP compute performance optimized for fixed-floating point computations including INT8 to fully meet the needs of AI inference
Up to 128 transceivers on device - backplane, chip-to-optics, chip-to-chip functionality
Gen3 x16 Integrated PCIe Block for 100G Applications
DDR4 supports up to 2,666Mb/s and up to 500Mb on-chip memory cache for greater efficiency and low latency
150G Interlaken, 100G Ethernet MAC core for high-speed connectivity
Virtex UltraScale+ HBM FPGAs offer the highest on-chip memory density, with up to 500Mb of total on-chip integrated memory and up to 16GB of,in-package integrated High Bandwidth Memory (HBM) Gen2, enabling 460GB/s memory bandwidth.Innovative embedded HBM controller and breakthrough integration provide maximum bandwidth, efficient routing and logic utilization, and Optimized power efficiency.
460GB/s memory bandwidth provides 20 times more bandwidth than DDR4 DIMMs. Expanded AXI ports and integrated port switches allow any port for any address access while minimizing design size, complexity, and time-to-market, resulting in the most available HBM bandwidth.
Multi-terabyte SerDes bandwidth
Up to 3.1Tb/s SerDes bandwidth for high throughput systems. Suppoconnectivity city4 and 32.75G NRZ transceivers enable support for the latest optical equipment and compatibility with existing infrastructure.
Integrated hard IP for 100G Ethernet with RS-FEC, 150G Interlaken, and PCIe Gen4 enables the lowest power consumption and faster design process.
Compared to discrete memory solutions, the power consumption per bit is reduced by a factor of 4 to 6 (approximately 7pJ per bit), which can reduce operating costs for power-sensitive use cases.
Cache-coherent computing with CCIX ports provides a complete end-to-end solution for multi-100G ports.
These FPGAs enable small system designs without compromising performance by eliminating I/O to external package memory and providing massive on-chip memorable.To help drive a new wave of Ethernet deployments, Xilinx has integrated 58Gb/s transceivers into its 16nhighinFET+ Virtex UltraScale+ FPGA family.
Virtex UltraScale+ 58G PAM4 FPGAs not only double bandwidth on existing infrastructure but also extend ASIC lifetime. These FPGAs offer the fastest transceivers available in hardware programmable devices and, in conjunction with new optical products, help users build future-proof systems.
Virtex UltraScale+ VU19P FPGAs not only support prototyping and simulation of the most advanced ASIC and SoC technologies but also facilitate the development of complex algorithms. The VU19P FPGA provides the highest logic density and the largest number of I/Os in a single chip Xilinx has ever seen, which can fully meet the latest needs of technological development.
The 9 million system logic cells not only help designers simulate and prototype larger, more complex designs but also create custom test logic for test equipment vendors.
The massive I/O bandwis not only ideal for interconnecting multiple FPGAs bu,t also allows engineers to connect a wide range of types and speeds of external memory for fast and deep storage of state information.
80 GTY (28Gb/s) transceivers provide up to 4.5Tb/s transceiver bandwidth, which is suitable for high port density test equipment, and next-generation platforms using emerging interface standards and protocols.
The lidless package provides an optimal thermal solution that helps designers push the limits of performance to the extreme. Deploying high-performance systems in thermally constrained environments is now easier memorable
FPGA agents provide more introductions about Virtex UltraScale+ devices and provide customers with a full range of services from professional technical support to overall solutions.