QPro Virtex-II Pro platform FPGAs are well-suited for designs based on IP cores and customized modules. The family incorporates the PowerPC CPU blocks in the Virtex-II Pro architecture. This family of FPGAs empowers complete solutions for telecommunication, wireless, networking, video, and DSP applications.
The Virtex-II Pro architecture and leading-edge 0.13 µm CMOS nine-layer copper process are optimized for high performance designs in a wide range of densities. Combining a wide variety of flexible features and IP cores, the QPro Virtex-II Pro family enhances programmable logic design capabilities and is a powerful alternative to maskprogrammed gate arrays.
QPro Virtex-II Pro devices are user-programmable gate arrays with various configurable elements and embedded blocks optimized for high-density and high-performance system designs. QPro Virtex-II Pro devices implement the following functionality:
Embedded IBM PowerPC 405 RISC processor blocks.
SelectIO-Ultra blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by the programmable IOBs.
Configurable Logic Blocks (CLBs) provide functional elements for combinatorial and synchronous logic, including basic storage elements. BUFTs (three-state buffers) associated with each CLB element drive dedicated segmentable horizontal routing resources.
Block SelectRAM+ memory modules provide large 18 Kb storage elements of True Dual-Port RAM.
Embedded multiplier blocks are 18-bit x 18-bit dedicated multipliers.
Digital Clock Manager (DCM) blocks provide selfcalibrating, fully digital solutions for clock distribution delay compensation, clock multiplication and division,and coarse- and fine-grained clock phase shifting.