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Xilinx Macrocell CMOS CPLD

Macrocell CMOS CPLD

The XC7336 is a high performance CPLD providing general purpose logic integration. It consists of four PAL-like 24V9 Fast Function Blocks interconnected by the 100% populated Universal Interconnect Matrix (UIMTM). 
The XC7336 is designed in 0.8 u CMOS EPROM technology, in speed grades ranging from 5 to 15 ns. The XC7336Q is also available now, providing lower power consumption in-10,-12 and-15 ns speed grades.

The XC7354 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like 24V9 Fast Function Blocks and four High Density Function Blocks interconnected by the 100%-populated Universal Interconnect Matrix (UIMâ„¢).

Power Management 

The XC7354 features a power-management scheme that permits non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often reduced significantly, since, in most systems only a few paths are speed critical. Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation.

Operating current for each design can be approximated for specific operating conditions using the following equation: 

pecific operating conditions using the following equation:
ICC (mA)=MCHP (3.0) + MCLP (2.6) +
MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)

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