CORE Generator system

Features

Simulation with SystemGenerator

1. Modules that must be included: Gateway In, Gateway Out, SystemGenerator, and Xilinx fixed-point arithmetic unit.

2. For external interface modules with precise clock limitation in system design, using System Generator design is not the best method. At this time, you can use HDL and other methods to implement, and then import it into the Sysgen project through the Black Box provided by the System Generator tool.

SystemGenerator Blockset

1. Mainly include: Xilinx Blockset, XilinxPreference Blockset and Xilinx XtremDSP Kit three library function blocks.

2. XilinxBlockset contains all the modules that build digital signal processing systems and other FPGA digital systems in Simulink.

3. XilinxPreferenceBlockset is a higher-level module, which is composed of modules in Xilinx Blockset, which reduces the development difficulty and has high reliability.

Signal data type

1. The output format of XilinxBlock can be set as: Fullprecision and User-defined precision

Fullprecision: Will automatically expand the bit width in the operation

User-definedprecision: Wrap or saturate the output result (user settings).

2. In SystemGenerator, click Format –>Port/Signal Displays –> Port Data Type to display the data type of each module's input and output.

3. When Simulink cannot determine the data type and sampling rate, an error will be reported, usually this situation occurs in the presence of feedback. At this time, the signal can be forced or redefined by adding an Assert module. And does not occupy hardware resources.

4. GatewayIn can set SamplePeriod, the larger the value, the fewer sampling points. Generally speaking, for the same group of Gateway In, the sample period should be the same, that is, the sampling rate is the same. So when modifying the Sample Period of a Gateway In, remember to update the Sample Period of the Gateway In of the same level at the same time.

5. Sampling rate conversion, using modules: Up sample and Down sample. Different colors in SystemGenerator represent different sampling rates. You can click Format –> Sample Time Colors

Using Matlab to generate test vectors

1. Use FromWorkspaceblock to generate test vectors. Note that the data must be a 2xn matrix:

colume1 = time values

colume2 = data values

For example: [1:101;sin(2*pi*[0:.01:1])]

2. Use the Toworkspace block to output sysgen data to MATLAB for analysis

Clock cycle

1. Simulinksystemperiod is the Simulink simulation clock period. This period must be the largest common factor of all sampling periods in the design. For example, there are 3 sampling periods (2, 3, 4) in the system, then Simulink system period is 1.

2. If the FPGA system clock period is 10 ns, then the Simulink system period, 2s, 3s, and 4s sampling periods respectively correspond to 10 ns, 20 ns, 30 ns, and 40 ns when the FPGA device is implemented. Another approach is to define the Simulink system cycle as the FPGA system cycle, thus eliminating the conversion between clock cycles.

3. The ClockEnable Probe module can be used to implement potential clock enable signals.