Chipscope is an online debugging software launched by XILINX. The price is cheap. It can completely adjust the timing without the traditional logic analyzer (too expensive), observe any signal inside the FPGA, and set the trigger condition, data width and depth. Convenient, but there are certainly deficiencies, such as speed and data volume. Chipscope itself is a logic analyzer, which is mainly used to collect and observe the internal signals of the chip during the upper board test process for easy debugging.
Its principle is to insert a core (including ILA and ICON) for data collection into your integrated netlist. You can use core inserter or core generator to insert data, but the latter needs to be in the source code. Instantiate. Using core inserter is faster, basically it is to select the signal you want to observe and the trigger source, clock, etc., and then it will automatically generate a new netlist file, and then use this netlist to place and route in the ISE to generate the download The file is downloaded to the chip to run through JTAG. During the operation of the chip, if the trigger source you select changes or meets the trigger conditions, the core in the chip will collect and store the signal you want to observe in the RAM (also FF) in the chip. Then upload the collected signal to the PC through the JTAG port, and finally display it as a waveform in the interface of the PC's chipscope analyzer, so you can see the signal waveform in the chip.
We usually use Chipscope's core inserter to implant Chipscope cores in our projects. Everything has its pros and cons. XILINX's Chipscope core inserter tool helps you easily insert the core into your project. There are certain disadvantages, that is, the compilation time is extended very long, and each time the compilation process, Will regenerate the ICON and ILA kernel netlist based on your cdc project file, and then recompile the entire project, then the compilation time will inevitably be extended.
Therefore, if you want to acquire the signal waveform you want, the first is that your trigger conditions are met. Chipscope does not change the signals in your original design, only collects them.
FPGA Spartan-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 900-Pin FBGA
FPGA Spartan-IIE Family 50K Gates 1728 Cells 357MHz 0.15um Technology 1.8V 208-Pin HSPQFP EP
FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 132-Pin CSBGA
FPGA XC5200 Family 16K Gates 1296 Cells 83MHz 0.5um Technology 5V 240-Pin PQFP