This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > Wiki encyclopedia > BUFT

BUFT

Three-state buffer (Three-state buffer), also known as three-state gate, three-state driver, its three-state output is controlled by the enable output, when the enable output is valid, the device realizes the normal logic state output (logic 0, Logic 1), when the enable input is invalid, the output is in a high-impedance state, which is equivalent to disconnecting from the connected circuit.

Tristate buffer

The buffer is one of the digital components. It does not perform any operation on the input value, and its output value is the same as the input value, but it plays an important role in the design of the computer.

There are two types of buffers, commonly used buffers (regular buffers) and tri-state buffers. The conventional buffer always outputs the value directly, and is used to output the current to the higher-level circuit system. In addition to the functions of conventional buffers, tri-state buffers also have an optional cartoon input terminal, denoted by E. There are different output values when E=0 and E=1.

The buffer can be divided into input buffer and output buffer. The former's role is to temporarily store the data sent by the peripheral device so that the processor can take it away; the latter's role is to temporarily store the data sent by the processor to the peripheral device. With the NC buffer, you can make the high-speed CPU and slow-working peripherals coordinate and buffer, and synchronize data transmission. Because the buffer is connected to the data bus, it must have a three-state output function.

When E=1, the gate is selected, and its input is directly sent to the output;

If E=0, the buffer is blocked, no matter what value is input, the output is always high impedance, denoted by Z. The high-impedance state allows the current to drop sufficiently low that the output of a similar buffer is not connected to anything.

EDA code

library ieee;

use IEEE.STD_LOGIC_1164.all;

ENTITY BUF3S IS

PORT (INPUT:IN STD_LOGIC;ENABLE:IN STD_LOGIC;OUTPUT:OUT STD_LOGIC);

END BUF3S;

ARCHITECTURE BHV OF BUF3S IS

BEGIN

PROCESS(ENABLE,INPUT)

BEGIN

IF ENABLE='1'

THEN OUTPUT<=INPUT;

ELSE OUTPUT<='Z';

END IF;

END PROCESS;

END BHV;

ASSOCIATED PRODUCTS

  • XC3S5000-4FGG1156C

    XC3S5000-4FGG1156C

    FPGA Spartan-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 1156-Pin FBGA

  • XC2S50E-6FT256I

    XC2S50E-6FT256I

    FPGA Spartan-IIE Family 50K Gates 1728 Cells 357MHz 0.15um Technology 1.8V 256-Pin FTBGA

  • XCS05-4PC84C

    XCS05-4PC84C

    FPGA Spartan Family 5K Gates 238 Cells 166MHz 5V 84-Pin PLCC

  • XC3S500E-4CFGG320D

    XC3S500E-4CFGG320D

    Xilinx BGA

  • XC3S500E-4FG320I

    XC3S500E-4FG320I

    FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm Technology 1.2V 320-Pin FBGA

FPGA Tutorial Lattice FPGA
Need Help?

Support

If you have any questions about the product and related issues, Please contact us.