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Another special resource in FPGA-DCM (Digital Clock Manager). The DCM contains a DLL (Delay-Locked Loop), which can provide the function of double and divide the clock signal, and can maintain the phase relationship between the output clocks, that is, zero clock deviation.

Therefore, for the frequency-divided clock, the frequency-dividing function of DCM can be directly used, thereby eliminating the frequency-dividing register, and thoroughly solving the clock deviation between CLK_2X and CLK_1X. However, a more suitable option is to use the frequency multiplication function of DCM, so only need to prepare a low frequency clock input of 40MHz for FPGA, which is easier to implement than 80MHz.

Through the use of BUFGMUX and DCM, the following figure after transformation can be obtained.


Structure diagram after DCM transformation

After the transformation, only one DCM and one BUFGMUX pass between the clock signal of each clock domain and the signal source CLK_IN, and the clock deviation between them is only the clock deviation of the clock network itself and the output of the DCM to each BUFGMUX input. Line delay deviation. If further optimized, by placing a position constraint on BUFGMUX at the place of routing, the four BUFGMUX are forced to be on the eight BUFGMUX above or below the FPGA. The clock deviation across the clock domain can be controlled in the VIRTEX-II 6000 FPGA. Within 0.5ns, basically meet the requirements of 80MHz. The post-imitation waveform of the modified clock circuit is shown in Figure 7, and its maximum clock deviation is 0.722 ns.


Picture 7

In fact, DCM and BUFGMUX have been the standard components of FPGA since VIRTEX-II, and can be directly used on SPARTAN-3, VIRTEX-II, VIRTEX-II PRO, VIRTEX-4 and other devices, so the circuit structure can also be corresponding Generalized to the circuit design of these FPGAs.

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