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BSDL (Boundary Scan Description Language) files are required for board-level and system-level testing and in-system programming using boundary scan. BSDL files describe the IEEE 1149.1 or JTAG design spreadsheets in an IC. These files are provided by IC vendors as part of their device specifications.


"Boundary scan" is a testability design technique, that is, the test problem is considered in the design stage of the electronic system.

BSDL (boundary scan des cription language) is a subset of language hardware description language (VHDL), which is a description of the boundary scan characteristics of boundary scan devices. It is mainly used to communicate the relationship between boundary scan device manufacturers, users and test tools. Its applications include: manufacturers provide BSDL descriptions as part of boundary-scan devices to users; BSDL descriptions provide relevant information for automatic test pattern generation (ATPG) tools to test specific circuit boards; generation under the support of BSDL is defined by the IEEE1149.1 standard Test logic. Now, the BSDL language has officially become an attachment to the IEEE1149.1 standard document. BSDL itself is not a general hardware description language, but it can be combined with software tools for test generation, result analysis, and fault diagnosis. Each boundary scan device is accompanied by a specific BSDL description file.

TAP integrity test

The command capture (INSTRUCTION_CAPTURE) attribute provides a way to test the integrity of the TAP. The TAP integrity test can detect whether the input terminals of the clock TCK and mode selection TMS are connected correctly, and the related signals provided are normal; whether the data input TDI and data output TDO terminals are connected correctly, and whether the input and output functions are normal; internal Whether the instruction register works normally; whether the internal boundary scan register works normally. The TAP integrity test is the recommended test operation before any other boundary scan tests to ensure that the boundary scan chain can work properly.

The process of TAP integrity test is shown in Figure 3. In the TAP's Shift-IR state, the instruction capture bit pattern has been loaded into the shift register portion of the instruction register, and the data is directly removed from TDO and compared with the capture bit pattern of each chip. If the data are consistent, the TAP integrity test passes.

Chip ID code detection

The chip ID code is the identification code of the built-in device that identifies the chip. The chip can be identified by detecting the chip ID code to determine whether the chip is assembled correctly, and can further determine whether the chip model, manufacturer and version number are consistent with its identification, and identify the chip Authenticity. When the TAP enters the Test-Logic-Reset state, if the flag register exists, it is forcibly connected between TDI and TDO, the value of the register LSB is "1", otherwise, the bypass register is connected between TDI and TDO, The value of the register is "0". Therefore, when detecting the value of the chip flag register, you can directly enter the shift data state from the reset state, output the value of TDO, and determine whether the first bit is "1". If it is, then the chip has a standard register. Continue to move out the other 31 digits, and make judgments and displays. The detection process is shown in Figure 4. When we check the ID identification code of the chip EPM7128SL84, the output waveform of the TDO terminal collected by the logic analyzer is shown in Figure 5, which is consistent with the ID code in the BSDL description, indicating that the device is correct.

Boundary scan interconnect test

In the process of developing the boundary scan test software, we designed and manufactured a test circuit board based on the boundary scan mechanism as a diagnostic experiment object. Among them, there are 16 interconnection networks between the two EPM7128SL84 chips, which are the interconnection between the 4-12 pins and 33-41 pins of the two chips (excluding the 7-pin ground wire and 38-pin power wire). When performing interconnection testing, first construct a 16×16 test matrix, and then load the 16 column vectors of this matrix to the IO4~IO12, IO33~IO41 pins of chip 1 (except 7 and 38 pins) , And then execute the external test instruction. The signal on the corresponding pin is captured by chip 2 to form a response vector. After all 16 column vectors have been loaded and captured separately, the response matrix is then diagnosed [3], as shown in Figure 6. During this test, the vector data loaded on the IO pins of chip 1 must be located to the tri-state output unit corresponding to each pin, that is, 281, 278, 275, 269, 263, 260, 257, 251 of chip 1 , 179, 173, 167, 164, 161, 155, 149, 146 units; and the signals on the corresponding pins captured by the chip 2 are placed into the input unit corresponding to each pin after the sampling instruction is executed, That is chip 279,276,273,267,261,258,255,249,177,171,165,162,159,153,147,144 units. In this way, the data of the corresponding unit output from the TDO constitutes a response matrix, and the response matrix is analyzed according to a certain algorithm to detect sluggish, short circuit, open circuit and bridge faults.


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