This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > Wiki encyclopedia > ATPG


APT is a program development language. Automatic Test Pattern Generation (ATPG) automatic test vector generation is a process in which test pattern vectors used in the testing of semiconductor appliances are automatically generated by the program. The test vectors are sequentially loaded on the input pins of the device, and the output signals are collected and compared with the budgeted test vectors to judge the test results. ATPG effectiveness is an important indicator to measure test error coverage.



The automatic test pattern generation (English: Automatic Test Pattern Generation, ATPG) system is a tool that generates data for testing digital circuits after manufacture.

It is very difficult to achieve a very high fault coverage for the test platform of very large scale integrated circuits because of its high complexity. For circuit testing of combinatorial logic and sequential logic, different ATPG methods must be used.


An ATPG cycle can be divided into two stages:

1. Test generation

2. Test application

During the test generation process, the test model for the circuit design is generated in the Gate or Transistor Level, so that the wrong circuit can be detected by the model. This process is basically a mathematical process and can be obtained by the following methods:

1. Manual method

2. Algorithm generation

3. Pseudo-random generation-the software generates test pattern vectors through complex ATPG procedures

When creating a test, our goal should be to execute efficient test graphics vectors in a limited storage space. It can be seen that ATPG needs to generate as few test vectors as possible under the condition of satisfying a certain error coverage rate. Mainly consider the following factors:

1. The time required to establish the minimum test group

2. The size of the test graphics vector, the requirements of software and hardware

3. The length of the test process

4. The time required to load the test graphics vector

5. External equipment


ATPG algorithms that are widely used now include: D algorithm, PODEM algorithm and FAN algorithm. Any algorithm requires a technique called "path sensitization", which refers to finding a path in a circuit so that the errors in the path can appear at the output of the path.

The most widely used algorithm is the D algorithm, D stands for 1 and D'stands for 0, and D and D'are complementary. The specific method will not be repeated here.

The ATPG generation process includes the following steps:

1. Wrong selection, select the error that needs to be tested

2. Initially, find a suitable set of input vectors

3. Transmission vector set

4. Comparison results

Testability design

Design for testability (English: Design for Testability, DFT) is an integrated circuit design technology that implants some special structures into the circuit at the design stage so that the design can be tested after completion. Circuit testing is sometimes not easy, because many internal node signals of the circuit are difficult to control and observe externally. By adding testability design structures, such as scan chains, internal signals can be exposed to the outside of the circuit. In short, although adding these structures in the design stage increases the complexity of the circuit and seems to increase the cost, it can often save more time and money in the test stage.


  • XC3042A-7PCG84C


    FPGA XC3000 Family 3K Gates 144 Cells 113MHz 5V 84-Pin PLCC

  • XC5210-3PQ240C


    FPGA XC5200 Family 16K Gates 1296 Cells 83MHz 0.5um Technology 5V 240-Pin PQFP

  • XC3S5000-4FG676I


    FPGA Spartan-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA

  • XC3S5000-4FGG676C


    FPGA Spartan-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA

  • XC2S50E-6PQ208C


    FPGA Spartan-IIE Family 50K Gates 1728 Cells 357MHz 0.15um Technology 1.8V 208-Pin HSPQFP EP

FPGA Tutorial Lattice FPGA
Need Help?


If you have any questions about the product and related issues, Please contact us.