ABEL: Advanced Boolean Equation Language, one of the three commonly used hardware description languages (ABEL, VHDL, Verilog). Use it to describe logic functions, which is convenient for designers to use PLD (compilable logic devices) to implement function functions.
The ABEL program is a text file containing some elements:
×Documents, including program names and comments
×Identification of input and output of logic function
×Statement used to specify the logic function to be implemented
×Type description of PLD or other target devices implementing logic function
× Used to specify the “test vector” that the logic function expects to output under certain input conditions.
FPGA XC5200 Family 10K Gates 784 Cells 83MHz 0.5um Technology 5V 208-Pin PQFP
FPGA XC4000E Family 25K Gates 2432 Cells 0.35um Technology 5V 304-Pin HSPQFP EP
FPGA XC3000 Family 3K Gates 144 Cells 113MHz 5V 100-Pin PQFP
FPGA Spartan-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 1156-Pin FBGA
FPGA Spartan-3 Family 5M Gates 74880 Cells 630MHz 90nm Technology 1.2V 900-Pin FBGA
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