Crossbar

Evolution

1. Bus-type switching architecture

The initial Ethernet switch was built on the basis of a shared bus. The exchange capacity that the shared bus structure can provide is limited, on the one hand, because the shared bus inevitably internal conflicts; on the other hand, the load effect of the shared bus makes the design of high-speed bus relatively difficult. With the user's desire for "exclusive bandwidth", this shared bus structure quickly developed into a shared memory structure.

The shared memory structure of the switch uses a large amount of high-speed RAM to store the input data, while relying on the central switching engine to provide a full-port high-performance connection. The core engine checks each input packet to determine the route. This type of switch is relatively easy to implement in design, but when the switching capacity is extended to a certain extent, memory operations will cause delays. In addition, in this design, it is relatively complicated to add redundant switching engines due to the problem of bus interconnection. Providing dual engines is relatively difficult to be very stable. Therefore, we can see that the network core switches introduced in the market in the early days are often single engines, especially as the switch ports increase, due to the need for larger memory capacity and faster speed, the price of central memory becomes very high. The swap engine will become a bottleneck for performance.

2. CrossBar+ shared memory architecture

As the switching capacity of network core switches has grown from dozens of Gbps to hundreds of Gbps today, a switching mode called CrossBar has gradually become the first choice for network core switches. CrossBar (CrossPoint) is called crossbar switch matrix or crossbar switch matrix. It can make up for some of the shortcomings of the shared memory model.

First, the CrossBar implementation is relatively simple. The physical connection from the line card to the switching structure in the shared switching architecture is simplified to a point-to-point connection, which is more convenient to implement, thereby making it easier to ensure the stability of large-capacity switches;

Secondly, there is no obstruction inside CrossBar. With a CrossBar, as long as multiple crosspoints are closed at the same time, multiple different ports can simultaneously transmit data. In this sense, we believe that all CrossBars are non-blocking internally because it can support all ports to exchange data at the same time at wire speed. In addition, due to its simple implementation principle and non-blocking switching structure, it can run at a very high rate. Semiconductor manufacturers can already use traditional CMOS technology to manufacture point-to-point serial transceiver chips with rates above 10Gbit/s.

Basically, the network core switches that appeared after 2000 basically chose the ASIC chip of CrossBar structure as the core. However, due to the cost of the Crossbar chip and many other factors, almost all the core switching equipment at this time chose the shared memory method to design the business board. In order to reduce the cost of the whole machine, "CrossBar + shared memory" has become a more common core switching architecture. However, under this structure, there will still be Crossbar interconnection problems between the bus of the service board and the switching network board. Because the data on the bus of the business board is a standard Ethernet frame, and generally Crossbar adopts the mode of cell exchange to reflect the efficiency and performance of Crossbar. Therefore, the structure of the shared bus used on the business board affects the efficiency of Crossbar to a certain extent, and the performance of the whole machine is completely limited by the performance of the Crossbar of the switching network board.

3. Distributed CrossBar architecture

When the switching capacity of the network core switch has developed to hundreds of Gbps, and supports multiple 10 Gigabit interfaces at the same time and is widely used in the backbone of the metropolitan area network and the core of the campus network, the distributed Crossbar architecture is well solved in the new The challenges of high performance and flexibility faced by network core switches in the application environment.

In other words, in addition to the Crossbar architecture used for the switching network board, the Crossbar+switch chip architecture is also adopted for each business board. Adding a switching chip on the business board can solve the problem of local switching, and the Crossbar chip between the switching chip and the switching network board of the business board solves the problem of cellizing the business data of the business board, thereby improving the switching efficiency. And make the data type of the service board and the cells of the switching network board become two planes, that is to say, there can be a very rich service board, such as the integration of firewall, IDS system, router, content exchange, IPv6 and other types of services To the core switching platform, which greatly improves the business expansion capability of the network core switch. At the same time, this Crossbar has a corresponding high-speed interface that is connected to two main control boards or switching network boards, thereby greatly improving the speed of the dual main control main and standby switching.

In the distributed Crossbar design, the CPU also uses a distributed design. The main CPU on the main control board of the device is responsible for overall control scheduling, routing table learning and delivery; the slave CPU of the service board is mainly responsible for local table lookup and service board state maintenance. This realizes distributed routing calculation and distributed routing table query, which greatly eases the pressure on the main control board and improves the forwarding efficiency of the switch, which is also an important reason why the local forwarding of the business board can improve the efficiency. This distributed Crossbar and distributed switching design concept is the development direction of the core network device design, ensuring that the network core can support the future massive data exchange and flexible multi-service support needs.